76
ATmega8515(L)
2512A–AVR–04/02
on the pin will causeaninterrupt requestevenifINT1 isconfigured as an output. The
corresponding interruptofExternalInterruptRequest1is executedfrom the INT1 Inter-
ruptVector.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit isset (one) and the I-bit in the Status Register(SREG) isset (one),
theexternalpin interruptis enabled.The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU GeneralControl Register (MCUCR)define whether theexternal
interruptis activated on rising and/orfalling edge of the INT0 pin orlevelsensed.Activity
on the pin will causeaninterrupt requestevenifINT0 isconfigured as an output. The
corresponding interruptofExternalInterruptRequest0is executedfrom the INT0 Inter-
ruptVector.
• Bit 5 – INT2: External Interrupt Request 2 Enable
When the INT2 bit isset (one) and the I-bit in the Status Register(SREG) isset (one),
theexternalpin interruptis enabled.The Interrupt Sense Control2 bit (ISC2) in the MCU
Control andStatus Register(MCUCSR)defineswhether theexternal interruptis acti-
vated on rising orfalling edge of the INT2 pin. Activity on the pin will causeaninterrupt
requestevenifINT2 isconfigured as an output. The corresponding interruptofExternal
InterruptRequest2is executedfrom the INT2 InterruptVector.
General Interrupt Flag
Register – GIFR
• Bit 7 – INTF1: External Interrupt Flag 1
When an edge orlogicchange on the INT1 pin triggers an interrupt request,INTF1
becomesset (one). If the I-bit in SREG and the INT1 bit in GICRare set (one), the MCU
will jump to the corresponding InterruptVector.The flag isclearedwhen theinterrupt
routine is executed.Alternatively, the flag can be clearedbywriting a logical one to it.
Thisflag is always clearedwhen INT1 isconfigured as a level interrupt.
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge orlogicchange on the INT0 pin triggers an interrupt request,INTF0
becomesset (one). If the I-bit in SREG and the INT0 bit in GICRare set (one), the MCU
will jump to the corresponding InterruptVector.The flag isclearedwhen theinterrupt
routine is executed.Alternatively, the flag can be clearedbywriting a logical one to it.
Thisflag is always clearedwhen INT0 isconfigured as a level interrupt.
• Bit 5 – INTF2: External Interrupt Flag 2
When an event on the INT2 pin triggers an interrupt request,INTF2 becomesset (one).
If the I-bit in SREG and the INT2 bit in GICRare set (one), the MCU will jump to the cor-
responding InterruptVector.The flag isclearedwhen theinterrupt routine is executed.
Alternatively, the flag can be clearedbywriting a logical one to it. Note that when enter-
ing some sleep modeswith the INT2 interrupt disabled, theinput buffer on thispin will
be disabled.This maycausealogicchange in internalsignals which will set the INTF2
flag. See “DigitalInput EnableandSleepModes”onpage 60 for moreinformation.
Bit 76543 210
INTF1 INTF0 INTF2
– – – – –GIFR
Read/Write R/W R/W R/W RRRRR
Initial Value00000000
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