Rainbow-electronics ATmega8515L Manual do Utilizador descarregar pdf (Página 25)

ATmega8515(L)

2512A–AVR–04/02

time for theexternal memory in conjunction with the set-uprequirement of the

ATmega8515. Theaccess time for theexternal memory isdefined to bethetimefrom

receiving the chipselect/address until the data of this address actually isdriven on the

bus.Theaccess time cannot exceed thetimefrom theALE pulseis assertedlow until

data must be stable during a readsequence (t

LLRL

+ t

RLRH

- t

DVRH

in Table 99 to Table

106 on page 201).The different wait states are set up in software. As an additionalfea-

ture, it ispossibletodividetheexternal memory spaceintwo sectors with individualwait

state settings.This makes it possibletoconnecttwo different memory deviceswithdif-

ferent timing requirements to the same XMEM interface. ForXMEMinterface timing

details, please refer to Figure89 to Figure 92, and Table 99 to Table106.

Note that the XMEM interfaceis asynchronous and that the waveforms in the figures

below are related to theinternal system clock.The skewbetween the Internal andExter-

nalclock (XTAL1) is not guaranteed(it variesbetween devices, temperature, andsupply

voltage). Consequently, the XMEM interfaceis not suitedforsynchronous operation.

Figure 13. ExternalData Memory Cycleswithout Wait State (SRWn1 = 0and

SRWn0 = 0)

(1)

Note: 1. SRWn1 =SRW11 (uppersector) orSRW01 (lowersector), SRWn0 =SRW10 (upper

sector) orSRW00 (lowersector)

TheALE pulseinperiod T4 is only present if thenextinstruction accesses theRAM

(internal or external).

ALE

T1 T2 T3

Write

Read

A15:8

AddressPrev. Addr.

DA7:0

Address DataPrev. Data XX

DA7:0 (XMBK = 0)

DataPrev. Data Address

DA7:0 (XMBK = 1)

System Clock (CLK

CPU

)

1 2 ... 20 21 22 23 24 25 26 27 28 29 30 ... 222 223

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