Rainbow-electronics ATmega8515L Manual do Utilizador Página 129

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129
ATmega8515(L)
2512A–AVR–04/02
SPI Status Register SPSR
Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer iscomplete, the SPIF flag isset. An interruptis generated ifSPIE
in SPCRisset and global interrupts are enabled. If SS
is an input and isdriven low
when the SPI is in Master mode, thiswill also set the SPIF flag. SPIF isclearedbyhard-
ware when executing the corresponding interrupt handling vector.Alternatively, the
SPIF bit isclearedbyfirst reading the SPIStatus RegisterwithSPIF set, then accessing
the SPIData Register(SPDR).
Bit 6 – WCOL: Write COLlision Flag
The WCOL bit isset if the SPIData Register(SPDR) iswritten during a data transfer.
The WCOL bit (and the SPIF bit) are clearedbyfirst reading the SPIStatus Register
withWCOLset, and then accessing the SPIData Register.
Bit 5..1 – Res: Reserved Bits
These bits are reservedbits in the ATmega8515 andwill always read aszero.
Bit 0 – SPI2X: Double SPI Speed Bit
When thisbit iswritten logic one the SPIspeed(SCKFrequency) will be doubledwhen
the SPI is in Master mode (see Table58).This means that the minimum SCK periodwill
betwo CPUclock periods. When the SPI isconfigured asSlave, the SPI is only guaran-
teed to work at f
osc
/4 orlower.
The SPI interfaceonthe ATmega8515 is alsousedforprogram memory andEEPROM
downloading or uploading. See page 189forSerial Programming and verification.
SPI Data Register – SPDR
The SPIData Register is a read/write register usedfordata transferbetween the Regis-
terFileand the SPIShift Register. Writing to the register initiatesdata transmission.
Reading the registercauses the Shift Register Receive buffer to be read.
Bit 76543 210
SPIFWCOL–––––SPI2X SPSR
Read/WriteRRRRRRRR/W
Initial Value00000000
Bit 76543 210
MSB LSB SPDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value XXXXXXXXUndefined
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