Rainbow-electronics ATmega8515L Manual do Utilizador descarregar pdf (Página 16)

ATmega8515(L)

2512A–AVR–04/02

Figure 9. Data Memory Map

Data Memory Access Times Thissection describes the general access timing conceptsfor internal memory access.

Theinternaldata SRAM access isperformed in two clk

CPU

cycles asdescribed in Figure

10.

Figure 10. On-chipData SRAM Access Cycles

32 Registers

64 I/O Registers

Internal SRAM

(512 x 8)

$0000 - $001F

$0020 - $005F

$0260

$025F

$FFFF

$0060

Data Memory

External SRAM

(0 - 64K x 8)

clk

Data

Address

Address Valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction

Next Instruction

1 2 ... 11 12 13 14 15 16 17 18 19 20 21 ... 222 223

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