
58
ATmega8515(L)
2512A–AVR–04/02
enabledstate isfully acceptable, as a high-impedant environment will not noticethe dif-
ference between a strong highdriver and a pull-up. If this is not the case, thePUD bit in
the SFIOR Registercan be set to disableall pull-ups in all ports.
Switching between input withpull-up and output low generates the same problem. The
user mustuseeither thetri-state ({DDxn, PORTxn}=0b00) or the output highstate
({DDxn, PORTxn}=0b10) as an intermediate step.
Table24summarizes the controlsignals for the pin value.
ReadingthePinValue Independent of the setting ofData Direction bit DDxn, the port pin can be read through
thePINxn Registerbit. AsshowninFigure29, thePINxn Registerbit and the preceding
latch constitute a synchronizer.This is needed to avoid metastability if the physicalpin
changes value near theedge of theinternalclock, but it alsointroduces a delay. Figure
30 shows atimingdiagram of the synchronization when readinganexternally applied
pin value. Themaximum and minimum propagation delays are denoted t
pd,max
and t
pd,min
respectively.
Figure 30. Synchronization when Reading an Externally Applied Pin Value
Consider the clock periodstarting shortly
after
the first falling edge of the system clock.
The latch isclosedwhen the clock islow, and goes transparent when the clock ishigh,
as indicatedbythe shadedregion of the“SYNC LATCH” signal.The signal value is
latchedwhen the system clock goeslow. Itisclocked into thePINxn Register at the suc-
ceeding positive clock edge. As indicatedbythetwoarrows t
pd,max
and t
pd,min
, a single
Table 24. PortPinConfigurations
DDxn PORTxn
PUD
(in SFIOR) I/O Pull-up Comment
00 XInput NoTri-state (Hi-Z)
01 0Input Yes
Pxn will source current if ext. pulled
low.
01 1Input NoTri-state (Hi-Z)
10 XOutput No Output Low(Sink)
11 XOutput No Output High(Source)
XXX in r17, PINx
0x00 0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
t
pd, max
t
pd, min
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