
113
ATmega8515(L)
2512A–AVR–04/02
TheTimer/CounterOverflowFlag (TOV1) isset at the same timerclock cycleas the
OCR1x Registers areupdatedwith the double buffer value (at BOTTOM). When either
OCR1A orICR1 is usedfordefining theTOPvalue, the OC1A orICF1 flag set when
TCNT1 hasreached TOP. Theinterrupt flagscan then beused to generateaninterrupt
each time the counterreaches theTOPorBOTTOM value.
When changing theTOPvalue the program mustensurethat thenew TOPvalue is
higher or equal to thevalue of all of the compare registers. If theTOPvalue islower
than any of the compare registers, a comparematch will never occurbetween the
TCNT1 and the OCR1x.
AsFigure54shows the output generated is, in contrasttothe phase correctmode,sym-
metrical in all periods. Sincethe OCR1x Registers areupdated at BOTTOM, the length
of the rising and the falling slopeswill always beequal.This givessymmetrical output
pulses and is therefore frequency correct.
Using the ICR1 Registerfordefining TOP works well when using fixed TOPvalues. By
using ICR1, the OCR1A Register isfree to beusedfor generatingaPWM output on
OC1A. However, if the basePWM frequency is actively changedbychanging theTOP
value, using the OCR1A as TOPisclearly a betterchoice due to itsdouble buffer
feature.
In phaseandfrequency correctPWM mode, the compareunits allow generation of
PWM waveforms on the OC1xpins. Setting the COM1x1:0 bits to 2 will produce a non-
inverted PWM and an inverted PWM output can be generatedbysetting the COM1x1:0
to 3(See Table1onpage 117).TheactualOC1x value will only bevisibleonthe port
pin if the data direction for the port pin isset as output (DDR_OC1x).ThePWM wave-
formis generatedbysetting (orclearing) the OC1x Register at the comparematch
between OCR1x and TCNT1 when the counter increments, andclearing (orsetting) the
OC1x Register at comparematch between OCR1x and TCNT1 when the counterdecre-
ments.ThePWM frequency for the output when using phaseandfrequency correct
PWM can be calculatedbythe following equation:
The N variable represents the prescalerdivider(1, 8,64, 256, or 1024).
Theextreme valuesfor the OCR1x Registerrepresentsspecialcaseswhen generating
aPWM waveform output in the phase correctPWM mode. If the OCR1x isset equal to
BOTTOM the output will be continuously low and ifset equal to TOPtheoutput will be
set to highfor non-inverted PWM mode. For inverted PWM the output will have the
opposite logic values.
f
OCnxPFCPWM
f
clk_I/O
2 NTOP⋅⋅
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