166
ATmega8515(L)
2512A–AVR–04/02
Store Program Memory
Control Register – SPMCR
The StoreProgram Memory Control Registercontains the controlbits needed to control
the Boot Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit iswritten to one, and the I-bit in the Status Register isset (one), the
SPMready interrupt will beenabled.The SPMready interrupt will beexecuted aslong
as the SPMEN bit in the SPMCR Register iscleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-Programming (Page Eraseor Page Write) operation to theRWW section is
initiated, theRWWSB will be set (one)byhardware. When theRWWSB bit isset, the
RWW section cannot beaccessed.TheRWWSB bit will be cleared if theRWWSREbit
iswrittentooneafter a Self-Programming operation iscompleted.Alternatively the
RWWSB bit will automatically be cleared if a page load operation is initiated.
• Bit 5 – Res: Reserved Bit
Thisbit is a reservedbit in the ATmega8515 and always read aszero.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
When programming (page eraseorpage write) to theRWW section, theRWW section
isblockedforreading (theRWWSB will be set by hardware).Tore-enabletheRWW
section, theusersoftwaremust wait until the programming iscompleted(SPMEN will be
cleared).Then, if theRWWSREbit iswrittentooneatthe sametimeasSPMEN, the
next SPM instruction within fourclock cyclesre-enables theRWW section. TheRWW
section cannot be re-enabledwhilethe Flash isbusy with a Page Eraseor a Page Write
(SPMEN isset). If theRWWSREbit iswritten whilethe Flash isbeing loaded, the Flash
load operation will abortand the data loadedwill be lost.
• Bit3–BLBSET:BootLockBitSet
If thisbit iswritten to one at the same time asSPMEN, thenext SPM instruction within
fourclock cyclessetsBoot Lock bits, according to the data in R0. The datainR1and
theaddress in the Z-pointer are ignored.The BLBSET bit will automatically be cleared
upon completion of the Lock bit set, or if no SPM instruction is executedwithin fourclock
cycles.
An LPM instruction within three cycles after BLBSETandSPMEN are set in the SPMCR
Register, will read either the Lock bits or the Fuse bits(depending on Z0inthe Z-
pointer) into the destination register. See “Reading the FuseandLock Bitsfrom Soft-
ware” on page 170 fordetails.
• Bit2–PGWRT:PageWrite
If thisbit iswritten to one at the same time asSPMEN, thenext SPM instruction within
fourclock cycles executes Page Write,with the data stored in thetemporary buffer.The
page address is taken from the highpartof the Z-pointer.The datainR1and R0 are
ignored.ThePGWRT bit will auto-clear upon completion of aPageWrite, or if no SPM
instruction is executedwithin fourclock cycles.The CPU ishaltedduring theentire page
write operation if the NRWW section is addressed.
Bit 76543 210
SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN SPMCR
Read/Write R/W RRR/W R/W R/W R/W R/W
Initial Value000 0 0000
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