
46
ATmega8515(L)
2512A–AVR–04/02
Watchdog Reset When the Watchdog times out, it will generate a short reset pulseof one CK cycle dura-
tion. Onthe falling edge of thispulse, the delay timerstartscounting theTime-out period
t
TOUT
.Refer to page 50 fordetails on operation of the Watchdog Timer.
Figure 26. Watchdog Reset During Operation
MCU Control and Status
Register – MCUCSR
The MCU Control andStatus Registerprovides information on which reset source
caused an MCU Reset.
• Bit 3 – WDRF: Watchdog Reset Flag
Thisbit isset if a Watchdog Reset occurs.The bit isreset by aPower-on Reset, orby
writing a logiczerotothe flag.
• Bit 2 – BORF: Brown-out Reset Flag
Thisbit isset if a Brown-out Reset occurs.The bit isreset by aPower-on Reset, orby
writing a logiczerotothe flag.
• Bit1–EXTRF: External Reset Flag
Thisbit isset if an External Reset occurs.The bit isreset by aPower-on Reset, orby
writing a logiczerotothe flag.
• Bit 0 – PORF: Power-on Reset Flag
Thisbit isset if aPower-on Reset occurs.The bit isreset only by writing a logiczeroto
the flag.
To makeuseof the reset flags to identify a reset condition, theusershould read and
then reset the MCUCSRas early aspossibleinthe program. If the register iscleared
before anotherreset occurs, the sourceof the reset can be foundbyexamining the reset
flags.
CK
CC
Bit 76543 210
– – SM2 –WDRFBORFEXTRF PORF MCUCSR
Read/Write R/W R/W RR/W R/W R/W R/W R/W
Initial Value000 See Bit Description
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