
211
ATmega8515(L)
2512A–AVR–04/02
Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd ← Rd+Rr Z,C,N,V,H 1
ADC Rd, Rr Add withCarry twoRegisters Rd ← Rd+Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, RrSubtracttwo Registers Rd ← Rd-Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1
SBC Rd, RrSubtract withCarry two Registers Rd ← Rd-Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract withCarry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, RrLogical AND Registers Rd ← Rd • RrZ,N,V1
ANDI Rd, K Logical AND Register andConstant Rd ← Rd • KZ,N,V1
ORRd, RrLogicalORRegisters Rd ← Rd vRrZ,N,V1
ORI Rd, K LogicalORRegister andConstant Rd ← Rd v KZ,N,V1
EORRd, RrExclusive OR Registers Rd ← Rd ⊕ RrZ,N,V1
COM RdOne’sComplement Rd ← $FF − Rd Z,C,N,V1
NEG Rd Two’sComplement Rd ← $00 − Rd Z,C,N,V,H 1
SBRRd,K Set Bit(s) in Register Rd ← Rd v KZ,N,V1
CBRRd,K ClearBit(s) in Register Rd ← Rd • ($FF - K) Z,N,V1
INC RdIncrement Rd ← Rd+1 Z,N,V1
DEC RdDecrement Rd ← Rd − 1 Z,N,V1
TSTRd Test forZeroorMinus Rd ← Rd • RdZ,N,V1
CLRRdClear Register Rd ← Rd ⊕ RdZ,N,V1
SERRdSet Register Rd ← $FF None 1
MUL Rd, RrMultiply Unsigned R1:R0 ← RdxRrZ,C2
MULS Rd, RrMultiply Signed R1:R0 ← RdxRrZ,C2
MULSU Rd, RrMultiply SignedwithUnsigned R1:R0 ← RdxRrZ,C2
FMUL Rd, RrFractionalMultiply Unsigned R1:R0 ← (RdxRr) << 1 Z,C 2
FMULS Rd, RrFractionalMultiply Signed R1:R0 ← (RdxRr) << 1 Z,C 2
FMULSU Rd, RrFractionalMultiply SignedwithUnsigned R1:R0 ← (RdxRr) << 1 Z,C 2
BRANCH INSTRUCTIONS
RJMP k Relative Jump PC ← PC+k +1 None 2
IJMP Indirect Jump to (Z) PC ← ZNone 2
JMP kDirect Jump PC ← kNone 3
RCALL k Relative Subroutine Call PC ← PC+k+1 None 3
ICALL Indirect Call to (Z) PC ← ZNone 3
CALL k Direct Subroutine Call PC ← kNone 4
RET Subroutine ReturnPC ← STACK None 4
RETIInterruptReturnPC ← STACK I 4
CPSE Rd,RrCompare,Skip ifEqual if(Rd=Rr) PC ← PC+2or3 None 1/2/3
CPRd,RrCompareRd − RrZ,N,V,C,H 1
CPC Rd,RrCompare withCarry Rd − Rr − CZ,N,V,C,H 1
CPI Rd,K Compare RegisterwithImmediate Rd − KZ,N,V,C,H 1
SBRC Rr, b Skip ifBit in RegisterCleared if(Rr(b)=0) PC ← PC+2or3 None 1/2/3
SBRS Rr, b Skip ifBit in Register isSet if(Rr(b)=1) PC ← PC+2or3 None 1/2/3
SBIC P,b Skip ifBit in I/O RegisterCleared if(P(b)=0) PC ← PC+2or3 None 1/2/3
SBIS P,b Skip ifBit in I/O Register isSet if(P(b)=1) PC ← PC+2or3 None 1/2/3
BRBS s, k Branch ifStatusFlag Set if(SREG(s) = 1) then PC←PC+k + 1 None 1/2
BRBC s, k Branch ifStatusFlag Cleared if(SREG(s) = 0) then PC←PC+k + 1 None
1/2
BREQ k Branch ifEqual if(Z=1) then PC ← PC+k+1 None
1/2
BRNE k Branch ifNot Equal if(Z=0) then PC ← PC+k+1 None
1/2
BRCS k Branch ifCarry Set if(C=1) then PC ← PC+k+1 None
1/2
BRCC k Branch ifCarry Cleared if(C=0) then PC ← PC+k+1 None
1/2
BRSH k Branch ifSame orHigher if(C=0) then PC ← PC+k+1 None
1/2
BRLO k Branch ifLower if(C=1) then PC ← PC+k+1 None
1/2
BRMI k Branch ifMinus if(N=1) then PC ← PC+k+1 None
1/2
BRPLk Branch if Plus if(N=0) then PC ← PC+k+1 None
1/2
BRGE k Branch ifGreater orEqual, Signed if(N⊕ V= 0) then PC ← PC+k+1 None
1/2
BRLT kBranch ifLess Than Zero,Signed if(N⊕ V= 1) then PC ← PC+k+1 None
1/2
BRHS k Branch ifHalf Carry Flag Set if(H=1) then PC ← PC+k+1 None
1/2
BRHC k Branch ifHalf Carry Flag Cleared if(H=0) then PC ← PC+k+1 None
1/2
BRTSk Branch if T Flag Set if(T = 1) then PC ← PC+k +1 None
1/2
BRTCk Branch if T Flag Cleared if(T = 0) then PC ← PC+k+1 None
1/2
BRVSk Branch ifOverflowFlag isSet if(V = 1) then PC ← PC+k+1 None
1/2
BRVCk Branch ifOverflowFlag isCleared if(V = 0) then PC ← PC+k+1 None
1/2
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