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132

ATmega8515(L)

2512A–AVR–04/02

Figure 63. USART Block Diagram

(1)

Note: 1. Refer to Figure1onpage 2, Table 37 on page 70, and Table 31onpage 66 for

USART pin placement.

The dashedboxes in the block diagram separate thethree main parts of the USART

(listedfrom thetop): Clock Generator, Transmitter and Receiver. Controlregisters are

sharedbyall units.The clock generation logicconsists ofsynchronization logicfor exter-

nalclock input usedbysynchronousslave operation, and the baudrate generator.The

XCK (TransferClock) pin is only usedbySynchronous Transfer mode. TheTransmitter

consists of a single write buffer, a serialShiftRegister, parity generator andcontrollogic

forhandling different serialframe formats.The write buffer allows a continuous transfer

ofdata without anydelaybetween frames.TheReceiver is themost complexpartof the

USART module due to itsclock anddata recovery units.The recovery units areusedfor

asynchronousdata reception. Inaddition to the recovery units, theReceiver includes a

ParityChecker, controllogic, a ShiftRegister and atwo levelreceive buffer(UDR).The

Receiversupports the same frame formats as theTransmitter, andcan detect Frame

Error, Data OverRun and ParityErrors.

PARITY

GENERATOR

UBRR[H:L]

UDR (Transmit)

UCSRA UCSRB UCSRC

BAUD RATE GENERATOR

TRANSMIT SHIFT REGISTER

RECEIVE SHIFT REGISTER RxD

TxD

CONTROL

UDR (Receive)

CONTROL

XCK

DATA

RECOVERY

CLOCK

RECOVERY

CONTROL

PARITY

CHECKER

DATA BUS

OSC

SYNC LOGIC

Clock Generator

Transmitter

Receiver

1 2 ... 127 128 129 130 131 132 133 134 135 136 137 ... 222 223

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