Rainbow-electronics W90P710CDG Manual do Utilizador descarregar pdf (Página 95)

100

101

W90P710CD/W90P710CDG

Publication Release Date: September 19, 2006

- 95 - Revision B2

Cache Test Register 0 (CTEST0)

Cache test control register that configures the cache and tag ram testing enable or disable. In addition,

this register controls the built-in-self-test (BIST) function of SRAM.

CTEST0 0xFFF6_0000 R/W Cache test register 0 0x0000_0000

31 30 29 28 27 26 25 24

RESERVED

23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8

BISTEN RESERVED BST_GP3 BST_GP2 BST_GP1 BST_GP0

7 6 5 4 3 2 1 0

RESERVED CATEST

BITS DESCRIPTION

[31:16] RESERVED

[15] BISTEN

BIST mode enable

When set to “1”, BIST mode will be enabled, the selected memory

groups begins to be tested by BIST.

[14:12] RESERVED

[11] BIST_GP3

Memory group 3 is selected to test by BIST

When set to “1”, memory group 3, including data cache tag ram

way 0 and way 1, are selected to be tested by BIST.

[10] BIST_GP2

Memory group 2 is selected to test by BIST

When set to “1”, memory group 2, including program cache tag

ram way 0 and way 1, are selected to be tested by BIST.

[9] BIST_GP1

Memory group 1 is selected to test by BIST

When set to “1”, memory group 1, including data cache ram way 0

and way 1, are selected to be tested by BIST.

[8] BIST_GP0

Memory group 0 is selected to test by BIST

When set to “1”, memory group 0, including program cache ram

way 0 and way 1, are selected to be tested by BIST.

[7:0] RESERVED

** Note: The 4 memory groups can be selected and tested simultaneously by BIST.

1 2 ... 90 91 92 93 94 95 96 97 98 99 100 ... 551 552

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