
W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 247 - Revision B2
BITS DESCRIPTIONS
[31:5]
Reserved -
[4]
SD_IEN
SD Interrupt Status Enable
0=Disable SD_IS interrupt generation
1=Enable SD_IS interrupt generation
[3]
DAT0_IEN
SD DAT0 Level Transition Interrupt Status Enable
0=Disable DAT0_STS interrupt generation
1=Enable DAT0_STS interrupt generation
[2]
CD_IEN
CD# Interrupt Status Enable
0=Disable CD_IS interrupt generation
1=Enable CD_IS interrupt generation
[1]
DO_IEN
Data Output Interrupt Status Enable
0=Disable DO_IS interrupt generation
1=Enable DO_IS interrupt generation
[0]
DI_IEN
Data Input Interrupt Status Enable
0=Disable DI_IS interrupt generation
1=Enable DI_IS interrupt generation
SD Interface Interrupt Status Register (SDIISR)
Register Address R/W Description Reset Value
SDISR
0xFFF0_730C
R/W SD Interface Interrupt Status Register 0x0000_00XX
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
DAT1_IS_ SD_DATA0 DAT0_STS
7 6 5 4 3 2 1 0
CD_ R2_CRC7
CRC CRC-16 CRC-7
CD_IS DO_IS DI_IS
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