
W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 381 - Revision B2
31 30 29 28 27 26 25 24
IS31 IS30 IS29 IS28 IS27 IS26 IS25 IS24
23 22 21 20 19 18 17 16
IS23 IS22 IS21 IS20 IS19 IS18 IS17 IS16
15 14 13 12 11 10 9 8
IS15 IS14 IS13 IS12 IS11 IS10 IS9 IS8
7 6 5 4 3 2 1 0
IS7 IS6 IS5 IS4 IS3 IS2 IS1 RESERVE
BITS DESCRIPTIONS
[31:1]
ISx
This register identifies those interrupt channels whose are both active and
enabled.
ISx: Interrupt Status
Indicates the status of corresponding interrupt channel
0 = Two possibilities:
(1) The corresponding interrupt channel is inactive no matter
whether it is enabled or disabled;
(2) It is active but not enabled
1 = Corresponding interrupt channel is both active and enabled (can assert an
interrupt)
[0]
Reserved
Reserved
AIC IRQ Priority Encoding Register (AIC_IPER)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
AIC_IPER
0xFFF8_210C
R
Interrupt Priority Encoding Register
0x0000_0000
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 VECTOR 0 0
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