
W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 453 - Revision B2
BITS DESCRIPTIONS
[31:8]
RESERVED -
[7:0]
GTR
Guard Time Register value.
This register specifies number of stop bits appended in the end of
data byte.
Bit 7 ~ 0: Guard time values. Default to be 01h.
Smart Card Host Extended Control Register (SCHI_ECR)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
SCHI_ECR0 0xFFF8_501C R/W Extended Control Register 0 0x0000_0052
SCHI_ECR1 0xFFF8_581C R/W Extended Control Register 1 0x0000_0052
31 30 29 28 27 26 25 24
RESERVED
23 22 21 20 19 18 17 16
RESERVED
15 14 13 12 11 10 9 8
RESERVED
7 6 5 4 3 2 1 0
GTR[7:0]
31 30 29 28 27 26 25 24
RESERVED
23 22 21 20 19 18 17 16
RESERVED
15 14 13 12 11 10 9 8
RESERVED
PSCKFS2
PSCKF
S1
PSCKFS
0
7 6 5 4 3 2 1 0
Reserved SCKFS2 SCKFS1 SCKFS0 CLKSTP CLKSTPL Reserved
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