Rainbow-electronics W90P710CDG Manual do Utilizador descarregar pdf (Página 384)

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101

W90P710CD/W90P710CDG

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The AIC classifies the interrupt into FIQ and IRQ. This register indicates whether the asserted

interrupt is FIQ or IRQ. If both IRQ and FIQ are equal to 0, it means there is no interrupt occurred.

BITS DESCRIPTIONS

[31:2]

Reserved

[1]

IRQ

IRQ [1]: Interrupt Request

0 = nIRQ line is inactive.

1 = nIRQ line is active.

[0]

FIQ

FIQ [0]: Fast Interrupt Request

0 = nFIQ line is inactive.

1 = nFIQ line is active

AIC Mask Enable Command Register (AIC_MECR)

AIC_MECR

0xFFF8_2120

Mask Enable Command Register Undefined

31 30 29 28 27 26 25 24

MEC31 MEC30 MEC29 MEC28 MEC27 MEC26 MEC25 MEC24

23 22 21 20 19 18 17 16

MEC23 MEC22 MEC21 MEC20 MEC19 MEC18 MEC17 MEC16

15 14 13 12 11 10 9 8

MEC15 MEC14 MEC13 MEC12 MEC11 MEC10 MEC9 MEC8

7 6 5 4 3 2 1 0

MEC7 MEC6 MEC5 MEC4 MEC3 MEC2 MEC1 RESERVE

BITS DESCRIPTIONS

[31:1]

MEC

MEC x: Mask Enable Command

0 = No effect

1 = Enables the corresponding interrupt channel

[0]

Reserved

1 2 ... 379 380 381 382 383 384 385 386 387 388 389 ... 551 552

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