Rainbow-electronics W90P710CDG Manual do Utilizador Página 1

W90P710CD/W90P710CDG 32-BIT ARM7TDMI-BASED MCU Publication Release Date: September 19, 2006 - 1 - Revision B2 W90P710CD/W90P710CDG 16/32-bit

W90P710CD/W90P710CDG - 10 - 4-Channel PWM y Four 16-bit timers with PWM y Two 8-bit pre-scalers & Two 4-bit dividers y Programmable duty contr

W90P710CD/W90P710CDG - 100 - If the O=2’b00 indicates the CPU is the owner of Rx descriptor. After the CPU completes processing the frame, it modifie

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 101 - Revision B2 RXINTR [16]: Receive Interrupt The RXINTR indicates the frame

W90P710CD/W90P710CDG - 102 - Rx Descriptor Word 2 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 103 - Revision B2 6.5.1.2 Tx Buffer Descriptor 31 30 1615 3 2 1 0O Reserved

W90P710CD/W90P710CDG - 104 - CRCApp [1]: CRC Append The CRCApp control the CRC append during frame transmission. If CRCApp is enabled, the 4-bytes CR

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 105 - Revision B2 Tx Descriptor Word 2 31 30 29 28 27 26 25 24 CCNT Reser

W90P710CD/W90P710CDG - 106 - LC [23]: Late Collision The LC indicates the collision occurred in the outside of 64 bytes collision window. This means

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 107 - Revision B2 TXINTR [16]: Transmit Interrupt The TXINTR indicates the packe

W90P710CD/W90P710CDG - 108 - 6.5.2 EMC Register Mapping The EMC implements many registers and the registers are separated into three types, the cont

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 109 - Revision B2 Continued. REGISTER ADDRESS R/W DESCRIPTION RESET VALUECON

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 11 - Revision B2 y When reach middle and end address of destination address, a

W90P710CD/W90P710CDG - 110 - Continued. REGISTER ADDRESS R/W DESCRIPTION RESET VALUEStatus Registers (11) CTXDSA 0xFFF0_30CC R Current Transmi

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 111 - Revision B2 6.5.2.1 Register Details CAM Command Register (CAMCMR) The EMC

W90P710CD/W90P710CDG - 112 - Continued. BITS DESCRIPTIONS [2] ABP The Accept Broadcast Packet controls the broadcast packet reception. If ABP is en

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 113 - Revision B2 ECMP CCAM AUP AMP ABP RESULT 0 0 0 0 0 No Packet 0 0 0

W90P710CD/W90P710CDG - 114 - CAM Enable Register (CAMEN) The CAMEN controls the validation of each CAM entry. Each CAM entry must be enabled first be

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 115 - Revision B2 Continued. BITS DESCRIPTIONS [9] CAM9EN CAM entry 9 is enable

W90P710CD/W90P710CDG - 116 - CAM Entry Registers (CAMxx) REGISTER ADDRESS R/W DESCRIPTION RESET VALUECAM0M 0xFFF0_3008 R/W CAM0 Most Significant

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 117 - Revision B2 CAMxM 31 30 29 28 27 26 25 24 MAC Address Byte 5 (MSB)

W90P710CD/W90P710CDG - 118 - CAMxL 31 30 29 28 27 26 25 24 MAC Address Byte 1 23 22 21 20 19 18 17 16 MAC Address Byte 0 (LSB) 15 14

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 119 - Revision B2 BITS DESCRIPTIONS [31:0] Length/Type Length/Type Field of PA

W90P710CD/W90P710CDG - 12 - Operation Voltage Range y 3.0 ~ 3.6 V for IO Buffer y 1.62 ~ 1.98 V for Core Logic Operation Temperature Range y TBD Op

W90P710CD/W90P710CDG - 120 - Transmit Descriptor Link List Start Address Register (TXDLSA) The Tx descriptor defined in EMC is a link-list data struc

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 121 - Revision B2 31 30 29 28 27 26 25 24 RXDLSA 23 22 21 20 19 18

W90P710CD/W90P710CDG - 122 - BITS DESCRIPTIONS [31:25] Reserved - [24] SWR The SWR (Software Reset) implements a reset function to make the EMC retu

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 123 - Revision B2 Continued. BITS DESCRIPTIONS [17] EnSQE The Enable SQE Check

W90P710CD/W90P710CDG - 124 - Continued. BITS DESCRIPTIONS [8] TXON The Frame Transmission ON controls the normal packet transmission of EMC. If the

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 125 - Revision B2 Continued. BITS DESCRIPTIONS [2] ARP The Accept Runt Packet c

W90P710CD/W90P710CDG - 126 - 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 MIIData 7

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 127 - Revision B2 BITS DESCRIPTIONS [31:24] Reserved - [23:20] MDCCR The MDC Cl

W90P710CD/W90P710CDG - 128 - Continued. BITS DESCRIPTIONS [12:8] PHYAD The PHY Address keeps the address to differentiate which external PHY is the

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 129 - Revision B2 Management frame fields PRE ST OP PHYAD REGAD TA DATA IDL

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 13 - Revision B2 3. PIN DIAGRAM 8514050556080757065165160155150145175170VSS18KPI

W90P710CD/W90P710CDG - 130 - BITS DESCRIPTIONS [31:22] Reserved - [21:20] Blength The DMA Burst Length defines the burst length of AHB bus cycle w

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 131 - Revision B2 Transmit Start Demand Register (TSDR) If the Tx descriptor is

W90P710CD/W90P710CDG - 132 - 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RXMS 7 6

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 133 - Revision B2 BITS DESCRIPTIONS [31:25] Reserved - [24] EnTxBErr The Enab

W90P710CD/W90P710CDG - 134 - Continued. BITS DESCRIPTIONS [20] EnNCS The Enable No Carrier Sense Interrupt controls the NCS interrupt generation.

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 135 - Revision B2 Continued. BITS DESCRIPTIONS [16] EnTXINTR The EnTXINTR contr

W90P710CD/W90P710CDG - 136 - Continued. BITS DESCRIPTIONS [9] EnDEN The Enable DMA Early Notification Interrupt controls the DENI interrupt generat

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 137 - Revision B2 Continued. BITS DESCRIPTIONS [4] EnRXGD The Enable Receive G

W90P710CD/W90P710CDG - 138 - Continued. BITS DESCRIPTIONS [0] EnRXINTR The Enable Receive Interrupt controls the Rx interrupt generation. If EnRXINT

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 139 - Revision B2 BITS DESCRIPTIONS [31:25] Reserved - [24] TxBErr The Transm

W90P710CD/W90P710CDG - 14 - 4. PIN ASSIGNMENT Table 4.1 W90P710 Pins Assignment PIN NAME 176-PIN LQFP Clock & Reset ( 5 pins ) EXTAL (15M) 52

W90P710CD/W90P710CDG - 140 - Continued. BITS DESCRIPTIONS [21] TXABT The Transmit Abort Interrupt high indicates the packet incurred 16 consecutive

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 141 - Revision B2 Continued. BITS DESCRIPTIONS [18] TXCP The Transmit Completi

W90P710CD/W90P710CDG - 142 - Continued. BITS DESCRIPTIONS [14] CFR The Control Frame Receive Interrupt high indicates EMC receives a flow control f

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 143 - Revision B2 Continued. BITS DESCRIPTIONS [8] DFOI The Maximum Frame Lengt

W90P710CD/W90P710CDG - 144 - Continued. BITS DESCRIPTIONS [4] RXGD The Receive Good Interrupt high indicates the frame reception has completed. If t

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 145 - Revision B2 Continued. BITS DESCRIPTIONS [0] RXINTR The Receive Interrupt

W90P710CD/W90P710CDG - 146 - BITS DESCRIPTIONS [31:12] Reserved - [11] TXHA The Transmission Halted high indicates the next normal packet transmiss

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 147 - Revision B2 Missed Packet Count Register (MPCNT) The MPCNT keeps the numbe

W90P710CD/W90P710CDG - 148 - REGISTER ADDRESS R/W DESCRIPTION RESET VALUE MRPC 0xFFF0_30BC R MAC Receive Pause Count Register 0x0000_0000 31 3

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 149 - Revision B2 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 1

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 15 - Revision B2 Table 4.1 W90P710 Pins Assignment (Continued) PIN NAME 176-PIN

W90P710CD/W90P710CDG - 150 - BITS DESCRIPTIONS [31:16] Reserved [15:0] MREPC The MAC Remote Pause Count shows the current value of the down count

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 151 - Revision B2 Current Transmit Descriptor Start Address Register (CTXDSA) Th

W90P710CD/W90P710CDG - 152 - BITS DESCRIPTIONS [31:0] CTXBSA Current Transmit Buffer Start Address Current Receive Descriptor Start Address Regist

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 153 - Revision B2 31 30 29 28 27 26 25 24 CRXBSA 23 22 21 20 19 18

W90P710CD/W90P710CDG - 154 - BITS DESCRIPTIONS [31:23] RX_FSM RxDMA FSM [22] Reserved - [21:16] RXBuf_FSM Receive Buffer FSM [15:12] RXFetch_F

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 155 - Revision B2 BITS DESCRIPTIONS [31:24] TX_FSM TxDMA FSM [23:22] Reserved

W90P710CD/W90P710CDG - 156 - Finite State Machine Register 1 (FSM1) The FSM1 shows the current value of the FSM (Finite State Machine) of the functio

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 157 - Revision B2 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18

W90P710CD/W90P710CDG - 158 - Continued. CONFIG SIGNALS CONFIG SIGNALS 6’h06 R0_PTLE, RxStart, SFD, WasSFD, RxFrame, WrByte, Rx_OvFlow, 1’b0,R0_RBC

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 159 - Revision B2 Debug Mode MAC Information Register (DMMIR) The DMMIR keeps th

W90P710CD/W90P710CDG - 16 - Table 4.1 W90P710 Pins Assignment (Continued) PIN NAME 176-PIN LQFP AC97/I2S/PWM/UART3 ( 5 pins ) AC97_DATAI / I2S_DAT

W90P710CD/W90P710CDG - 160 - BITS DESCRIPTIONS [31:5] Reserved - [3:2] BistFail The BIST Fail indicates if the BIST test fails or succeeds. If the

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 161 - Revision B2 6.6 GDMA Controller The W90P710 has a two-channel general DMA

W90P710CD/W90P710CDG - 162 - 6.6.2 GDMA Register Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written REGISTER

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 163 - Revision B2 BITS DESCRIPTIONS [31] RESERVED - [30:28] TC_WIDTH nRTC/nW

W90P710CD/W90P710CDG - 164 - Continued BITS DESCRIPTIONS [19] AUTOIEN Auto initialization Enable 1’b0 = Disables auto initialization 1’b1 = Enables

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 165 - Revision B2 Continued BITS DESCRIPTIONS [11] SBMS Single/Block Mode Selec

W90P710CD/W90P710CDG - 166 - Continued BITS DESCRIPTIONS [4] DADIR Destination Address Direction 1’b0 = Destination address is incremented successiv

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 167 - Revision B2 Channel 0/1 Destination Base Address Register (GDMA_DSTB0, DMA

W90P710CD/W90P710CDG - 168 - BITS DESCRIPTIONS [31:24] Reserved - [23:0] TFR_CNT The TFR_CNT represents the required number of GDMA transfers. The

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 169 - Revision B2 Channel 0/1 Current Destination Register (GDMA_CDST0, GDMA_CDS

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 17 - Revision B2 Table 4.1 W90P710 Pins Assignment (Continued) NAME 176-PIN LQF

W90P710CD/W90P710CDG - 170 - 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CURENT_TFR_CNT [23:16] 15 14 13 12 11 10 9

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 171 - Revision B2 6.7 USB Host Controller The Universal Serial Bus (USB) is a

W90P710CD/W90P710CDG - 172 - Interrupt Processing Interrupts are the communication method for HC-initiated communication with the Host Controller Dr

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 173 - Revision B2 Continued. REGISTER ADDRESS R/W DESCRIPTION RESET VALUEOpenHC

W90P710CD/W90P710CDG - 174 - Host Controller Revision Register REGISTER OFFSET ADDRESS R/W DESCRIPTION RESET VALUE HcRevision 0xFFF0_5000 R Host Co

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 175 - Revision B2 BITS DESCRIPTION [31:11] Reserved Reserved. Read/Write 0&apo

W90P710CD/W90P710CDG - 176 - Host Controller Command Status Register REGISTER ADDRESS R/W DESCRIPTION RESET VALUE HcCommandStatus 0xFFF0_5008 R/W

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 177 - Revision B2 Host Controller Interrupt Status Register All bits are set by

W90P710CD/W90P710CDG - 178 - Continued. BITS DESCRIPTION [1] WDH WritebackDoneHead Set after the Host Controller has written HcDoneHead to HccaDoneH

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 179 - Revision B2 Continued. BITS DESCRIPTION [5] FNOE FrameNumberOverflowEnabl

W90P710CD/W90P710CDG - 18 - Table 4.1 W90P710 Pins Assignment (Continued) NAME 176-PIN LQFP SCHI/SD/XDMA ( 10 pins ) SC0_DAT / SD_CMD / GPIO [29]

W90P710CD/W90P710CDG - 180 - BITS DESCRIPTION [31] MIE MasterInterruptEnable Global interrupt disable. A write of ‘1’ disables all interrupts. [30]

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 181 - Revision B2 Host Controller Communication Area Register REGISTER ADDRESS

W90P710CD/W90P710CDG - 182 - Host Controller Control Head ED Register REGISTER ADDRESS R/W DESCRIPTION RESET VALUEHcControlHeadED 0xFFF0_5020 R/W

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 183 - Revision B2 Host Controller Bulk Head ED Register REGISTER OFFSET ADDRESS

W90P710CD/W90P710CDG - 184 - Host Controller Done Head Register REGISTER ADDRESS R/W DESCRIPTION RESET VALUE HcDoneHead 0xFFF0_5030 R/W Host Con

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 185 - Revision B2 BITS DESCRIPTION 31 FINTVT FrameIntervalToggle This bit is t

W90P710CD/W90P710CDG - 186 - Host Controller Frame Number Register REGISTER ADDRESS R/W DESCRIPTION RESET VALUE HcFmNumber 0xFFF0_503C R Host Contr

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 187 - Revision B2 BITS DESCRIPTION [31:14] Reserved Reserved. Read/Write 0&apo

W90P710CD/W90P710CDG - 188 - 31 30 29 28 27 26 25 24 POTPGT 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved OC

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 189 - Revision B2 Host Controller Root Hub Descriptor B Register This register i

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 19 - Revision B2 Table 4.1 W90P710 Pins Assignment (Continued) NAME 176-PIN LQF

W90P710CD/W90P710CDG - 190 - Host Controller Root Hub Status Register This register is reset by the USBRESET state. REGISTER OFFSET ADDRESS R/W DESCR

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 191 - Revision B2 Continued. BITS DESCRIPTION [1] OVRCI OverCurrentIndicator Th

W90P710CD/W90P710CDG - 192 - Continued. BITS DESCRIPTION [19] POCIC PortOverCurrentIndicatorChange This bit is set when OverCurrentIndicator changes

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 193 - Revision B2 Continued. BITS DESCRIPTION [3] CPS (Read) PortOverCurrentInd

W90P710CD/W90P710CDG - 194 - 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved S

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 195 - Revision B2 6.8.1 USB Endpoints It consists of four endpoints, designated

W90P710CD/W90P710CDG - 196 - BITS DESCRIPTIONS [31:9] Reserved [8] WakeUp 0: no effect. 1: Generating remote wake-up signal to drive a K-state on

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 197 - Revision B2 USB Class or Vendor command Register (USB_CVCMD) REGISTER ADD

W90P710CD/W90P710CDG - 198 - BITS DESCRIPTIONS [31:16] Reserved [15] RUM_CLKI Interrupt enable for RESUME (for clock is stopped) 0: Disable 1: En

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 199 - Revision B2 Continued. BITS DESCRIPTIONS [5] GCFGI Interrupt Enable Contr

W90P710CD/W90P710CDG - 2 - Revision History REVISION DATE COMMENTS A 2005/12/02 Draft A.1 2005/12/21 Modify the register definition A.2 2006/01/17

W90P710CD/W90P710CDG - 20 - 5. PIN DESCRIPTION Table 5.1 W90P710 Pins Description PIN NAME IO TYPE DESCRIPTION Clock & Reset EXTAL (15M) I 1

W90P710CD/W90P710CDG - 200 - BITS DESCRIPTIONS [31:16] Reserved [15] RUM_CLKS Interrupt status for RESUME (for clock is stopped) 0: No Interrupt

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 201 - Revision B2 Continued. BITS DESCRIPTIONS [6] GSTRS Interrupt Status for U

W90P710CD/W90P710CDG - 202 - 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RUM_CLKC R

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 203 - Revision B2 Continued. BITS DESCRIPTIONS [8] VENC Interrupt Status Clea

W90P710CD/W90P710CDG - 204 - 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved S

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 205 - Revision B2 Continued. BITS DESCRIPTIONS [3] INF4_EN USB Interface-4 Cont

W90P710CD/W90P710CDG - 206 - USB Control transfer-out port 1 (USB_ODATA1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUEUSB_ODATA1 0xFFF0601C R USB

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 207 - Revision B2 USB Control transfer-out port 3 (USB_ODATA3) REGISTER ADDRESS

W90P710CD/W90P710CDG - 208 - USB Control transfer-in data port 1 Register (USB_IDATA1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUEUSB_IDATA1 0xF

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 209 - Revision B2 USB Control transfer-in data port 3 Register (USB_IDATA3) REGI

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 21 - Revision B2 Table 5.1 W90P710 Pins Description (Continued) Pin Name IO Type

W90P710CD/W90P710CDG - 210 - BITS DESCRIPTIONS [31:2] Reserved [1] USB_DPS USB Bus D+ Signal Status 0: USB Bus D+ Signal is low 1: USB Bus D+ Si

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 211 - Revision B2 Continued. BITS DESCRIPTIONS [1] CV_STL USB Class and Vendor

W90P710CD/W90P710CDG - 212 - USB Configured Value Register (USB_CONFD) REGISTER ADDRESS R/W DESCRIPTION RESET VALUEUSB_CONFD 0xFFF06044 R/W US

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 213 - Revision B2 BITS DESCRIPTIONS [31] Reserved [30:29] EPA_TYPE Endpoint

W90P710CD/W90P710CDG - 214 - BITS DESCRIPTIONS [31:6] Reserved [6] EPA_ZERO Send zero length packet to HOST [5] EPA_STL_CLR CLEAR the Endpoin

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 215 - Revision B2 BITS DESCRIPTIONS [31:6] Reserved [5] EPA_CF_IE Endpoint

W90P710CD/W90P710CDG - 216 - Continued. BITS DESCRIPTIONS [2] EPA_ALT_IC Endpoint A alternate setting interrupt clear [1] EPA_TK_IC Endpoint A t

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 217 - Revision B2 USB Endpoint A Address Register (EPA_ADDR) REGISTER ADDRESS

W90P710CD/W90P710CDG - 218 - BITS DESCRIPTIONS [31:20] Reserved [19:0] EPA_LENTH Endpoint A transfer length USB Endpoint B Information Registe

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 219 - Revision B2 Continued. BITS DESCRIPTIONS [15:12] EPB_ALT Endpoint B alt

W90P710CD/W90P710CDG - 22 - Table 5.1 W90P710 Pins Description (Continued) Pin Name IO Type Description AC97/I2S/PWM/UART3 AC97_nRESET / I2S_MCLK /

W90P710CD/W90P710CDG - 220 - Continued. BITS DESCRIPTIONS [2] EPB_RDY The memory is ready for Endpoint B to access [1] EPB_RST Endpoint B reset

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 221 - Revision B2 USB Endpoint B Interrupt Clear Register (EPB_IC) REGISTER ADD

W90P710CD/W90P710CDG - 222 - 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 223 - Revision B2 BITS DESCRIPTIONS [31:0] EPB_ADDR Endpoint B transfer addre

W90P710CD/W90P710CDG - 224 - 31 30 29 28 27 26 25 24 Reserved EPC_TYPE EPC_DIR Reserved EPC_MPS 23 22 21 20 19 18 17 16 EPC_MPS 15

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 225 - Revision B2 USB Endpoint C Control Register (EPC_CTL) REGISTER ADDRESS R

W90P710CD/W90P710CDG - 226 - USB Endpoint C interrupt enable Register (EPC_IE) REGISTER ADDRESS R/W DESCRIPTION RESET VALUEEPC_IE 0xFFF06088 R/W

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 227 - Revision B2 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 1

W90P710CD/W90P710CDG - 228 - 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 229 - Revision B2 BITS DESCRIPTIONS [31:0] EPC_ADDR Endpoint C transfer addre

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 23 - Revision B2 Table 5.1 W90P710 Pins Description (Continued) Pin Name IO Type

W90P710CD/W90P710CDG - 230 - 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved EPA_XFER 15 14 13 12 11 10 9 8 E

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 231 - Revision B2 USB Endpoint B Remain transfer length Register (EPB_XFER) REGI

W90P710CD/W90P710CDG - 232 - BITS DESCRIPTIONS [31:10] Reserved [9:0] EPB_PKT Endpoint B remain packet length USB Endpoint C Remain transfer le

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 233 - Revision B2 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 1

W90P710CD/W90P710CDG - 234 - 6.9 SD Host Controller The SD host controller of W90P710 supports Secure Digital card devices (SD, MMC). The SD host-co

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 235 - Revision B2 SD host controller checks the associated CRC-16 bits and repor

W90P710CD/W90P710CDG - 236 - 6.9.2 Register Mapping REGISTER ADDRESS R/W DESCRIPTION RESET VALUESD Registers (6) SDGCR 0xFFF0_0000 R/W SD Global

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 237 - Revision B2 6.9.3 SD Register Description SD Gloal Control Register (SDGC

W90P710CD/W90P710CDG - 238 - Continued. BITS DESCRIPTIONS [3] DMARd DMA Read Enable Set this bit high enables the DMA to transfer data from external

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 239 - Revision B2 SD DMA Transfer Starting Address Register (SDDSA) REGISTER AD

W90P710CD/W90P710CDG - 24 - Table 5.1 W90P710 Pins Description (Continued) Pin Name IO Type Description SCHI/SD/XDMA SC0_RST / SD_DAT0 / GPIO [27]

W90P710CD/W90P710CDG - 240 - SD DMA Byte Count Register (SDBCR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUESDBCR 0xFFF0_7008 R/W SD DMA Byte Co

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 241 - Revision B2 BITS DESCRIPTIONS [31:7] Reserved - [6] ERRIEN Bus Error Int

W90P710CD/W90P710CDG - 242 - SD global Interrupt Status Register (SDGISR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUESDGISR 0xFFF0_7010 R/W SD

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 243 - Revision B2 SD BIST Register (SDBIST) REGISTER ADDRESS R/W DESCRIPTION

W90P710CD/W90P710CDG - 244 - SD Interface Control Register (SDICR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUESDICR 0xFFF0_7300 R/W SD Interface

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 245 - Revision B2 Continued. BITS DESCRIPTIONS [5] 74CLK_OE 74 Clock Cycle Outp

W90P710CD/W90P710CDG - 246 - SD Host interface Initial Register (SDHIIR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUESDHIIR 0xFFF0_7304 R/W SD H

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 247 - Revision B2 BITS DESCRIPTIONS [31:5] Reserved - [4] SD_IEN SD Interrupt

W90P710CD/W90P710CDG - 248 - BITS DESCRIPTIONS [31:11] Reserved - [10] DAT1_IS_ SD Interrupt Value Status 0 = SD interrupt at interrupt period. Wri

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 249 - Revision B2 Continued. BITS DESCRIPTIONS [2] CD_IS CD# Interrupt Status 0

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 25 - Revision B2 Table 5.1 W90P710 Pins Description (Continued) Pin Name IO Type

W90P710CD/W90P710CDG - 250 - SD Receive Response Token Register 0 (SDRSP0) REGISTER ADDRESS R/W DESCRIPTION RESET VALUESDRSP0 0xFFF0_7314 R SD R

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 251 - Revision B2 BITS DESCRIPTIONS [31:8] Reserved - [7:0] SD_RSP_TK1 SD Rece

W90P710CD/W90P710CDG - 252 - 31 30 29 28 27 26 25 24 FBuf0 23 22 21 20 19 18 17 16 FBuf0 15 14 13 12 11 10 9 8 FBuf0 7 6 5 4

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 253 - Revision B2 6.10 LCD Controller 6.10.1 Main Features STN LCD Display y

W90P710CD/W90P710CDG - 254 - 6.10.2 LCD Register MAP REGISTER ADDRESS R/W DESCRIPTION RESET VALUELCD Controller LCDCON 0XFFF0_8000 R/W LCD Contro

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 255 - Revision B2 LCD Register MAP, continued REGISTER ADDRESS R/W DESCRIPTION

W90P710CD/W90P710CDG - 256 - 6.10.3 LCD Special Register Description 6.10.3.1 LCD Controller LCD Control Register (LCDCON) REGISTER ADDRESS R/W DE

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 257 - Revision B2 Continued BITS DESCRIPTIONS [23] LCDMON8 Monochrome LCD has a

W90P710CD/W90P710CDG - 258 - Continued BITS DESCRIPTIONS [9:8] LCDBUS LCD Data output re-map( Only used at Sync-type High Color TFT) 00 = Databus is

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 259 - Revision B2 Sync-type TFT: Fig. 6.10.3.2 Sync-type TFT output format TV-

W90P710CD/W90P710CDG - 26 - Table 5.2 W90P710 176-pin LQFP Multi-function List PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3USB1.1 Host/De

W90P710CD/W90P710CDG - 260 - Monochrome STN with 4-bit data bus: Fig. 6.10.3.5 Monochrome STN output format - 1 Monochrome STN with 8-bit data bus:

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 261 - Revision B2 replaced with zero. Please refer to GPIO chapter to setting th

W90P710CD/W90P710CDG - 262 - BITS DESCRIPTIONS [31:19] Reserved Reserved [18] UNDREN2 FIFO2 UNDERRUN interrupt enable [17] UNDREN1 FIFO1 UNDE

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 263 - Revision B2 BITS DESCRIPTIONS [31:20] Reserved Reserved [18] UNDRIS2

W90P710CD/W90P710CDG - 264 - 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved UNDRIC2 UNDRIC1 AHBERIC 15 14 13 12

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 265 - Revision B2 6.10.3.3 LCD Pre-processing OSD Up-Scaling Factor Register (OS

W90P710CD/W90P710CDG - 266 - 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 267 - Revision B2 BITS DESCRIPTIONS [31:24] OSDVDNN An 8-bit value specifies th

W90P710CD/W90P710CDG - 268 - 6.10.3.4 LCD FIFOs Controller FIFO Control Register (FIFOCON) REGISTER ADDRESS R/W DESCRIPTION RESET VALUEFIFOCON

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 269 - Revision B2 Continued BITS DESCRIPTIONS [18] VDBPP18SW Video image 18bpp

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 27 - Revision B2 Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued)

W90P710CD/W90P710CDG - 270 - FIFO1 Parameter Register (FIFO1PRM) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE FIFO1PRM 0xFFF0_8028 R/W FIFO1

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 271 - Revision B2 31 30 29 28 27 26 25 24 F2STRIDE[15:8] 23 22 21 20

W90P710CD/W90P710CDG - 272 - BITS DESCRIPTIONS [31:0] FIFO1SADDR These bits indicate the source address of the bank location for the LCD frame buff

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 273 - Revision B2 BITS DESCRIPTIONS [31:16] FIFO1COLCNT These bits indicate

W90P710CD/W90P710CDG - 274 - 31 30 29 28 27 26 25 24 FIFO1CURADR[31:24] 23 22 21 20 19 18 17 16 FIFO1CURADR[23:16] 15 14 13 12 11

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 275 - Revision B2 FIFO1 Real Column Count Register (F1REALCULCNT) REGISTER ADD

W90P710CD/W90P710CDG - 276 - BITS DESCRIPTIONS [31:16] Reserved Reserved [15:0] F2REALCOLCNT These bits indicate the FIFO2 real column count per-l

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 277 - Revision B2 (BSWP=0, HSWP=0, BPP18SWP=1) D[31:18] D[17:0] 0000H Pixel 1

W90P710CD/W90P710CDG - 278 - 12bpp image format: (BSWP=0, HSWP=0) D[31:28] P[27:16] P[15:12] D[11:0] 0000H Dummy Bit Pixel 2 Dummy Bit Pixel

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 279 - Revision B2 4bpp image format: (BSWP=0, HSWP=0) D[31:28] P[27:24] D[23

W90P710CD/W90P710CDG - 28 - Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 Sy

W90P710CD/W90P710CDG - 280 - (BSWP=1, HSWP=0) 0000H D[31:30] P[29:28] D[27:26] D[25:24] D[23:22] D[21:20] D[19:18] D[17:16] Pixel 1 Pixel 2 Pi

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 281 - Revision B2 (BSWP=0, HSWP=0) 0000H D[31] P[30] D[29] D[28] D[27] D[26

W90P710CD/W90P710CDG - 282 - Fig. 6.10.5.7 FIFO parameter example If there is an image with size 480*480, 24bpp, stored in memory device with start

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 283 - Revision B2 N BPP W (WORD) 1 BPP (Black / White) X % 32 2 BPP (4 gray-le

W90P710CD/W90P710CDG - 284 - BITS DESCRIPTIONS [31:0] VDLUTENTY1 Theses bits define address of Lookup Table SRAM when Video pixel data is 00 = VDLU

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 285 - Revision B2 Video Lookup Table Entry Index 3 Register (VDLUTENTY3) REGIST

W90P710CD/W90P710CDG - 286 - BITS DESCRIPTIONS [31:0] VDLUTENTY4 Theses bits define address of Lookup Table SRAM when Video pixel data is 00 = VDLU

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 287 - Revision B2 OSD Lookup Table Entry Index 2 Register (OSDLUTENTRY2) REGISTE

W90P710CD/W90P710CDG - 288 - BITS DESCRIPTIONS [31:0] OSDLUTENTRY3 Theses bits define address of Lookup Table SRAM when OSD pixel data is 00 = OSDLU

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 289 - Revision B2 31 30 29 28 27 26 25 24 DP2[15:8] 23 22 21 20 19

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 29 - Revision B2 Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued)

W90P710CD/W90P710CDG - 290 - Dithering Pattern 3 Register (DITHP3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUEDITHP3 0xFFF0_8078 R/W Gray lev

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 291 - Revision B2 BITS DESCRIPTIONS [31:16] DP8 Recommended pattern value “4’’

W90P710CD/W90P710CDG - 292 - 31 30 29 28 27 26 25 24 DP12[15:8] 23 22 21 20 19 18 17 16 DP12[7:0] 15 14 13 12 11 10 9 8 DP11[15

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 293 - Revision B2 PIXEL DATA OF 4BPP IMAGE THE ADDRESS VALUE WHICH WILL INPUT LO

W90P710CD/W90P710CDG - 294 - 6.10.3.6 LCD Post-processing Dummy Display Color Pattern Register (DDISPCP) REGISTER ADDRESS R/W DESCRIPTION RESET VA

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 295 - Revision B2 31 30 29 28 27 26 25 24 VWYS[31:24] 23 22 21 20 19

W90P710CD/W90P710CDG - 296 - BITS DESCRIPTIONS [31:16] VWYE Video Window Y-End A 16-bit value specifies the vertical last pixel positions of the LC

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 297 - Revision B2 31 30 29 28 27 26 25 24 OSDWYE[15:8] 23 22 21 20 1

W90P710CD/W90P710CDG - 298 - BITS DESCRIPTIONS [31:24] Reserved Reserved [23:16] BLICNT OSD Blinking Cycle Time An 8-bit value specifies the OSD b

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 299 - Revision B2 BITS DESCRIPTIONS [31:24] Reserved Reserved [23:16] OSDRKYP

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 3 - Revision B2 Table of Contents- 1. GENERAL DESCRIPTION ...

W90P710CD/W90P710CDG - 30 - Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3Mem

W90P710CD/W90P710CDG - 300 - 6.10.3.7 LCD Timing Generation LCD Timing Control 1 Register (LCDTCON1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 301 - Revision B2 31 30 29 28 27 26 25 24 PPL[15:8] 23 22 21 20 19

W90P710CD/W90P710CDG - 302 - BITS DESCRIPTIONS [31:30] Reserved Reserved [29:20] VSPW Vertical sync pulse width determines the VSYNC pulse's h

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 303 - Revision B2 LCD Timing Control 5 Register (LCDTCON5) REGISTER ADDRESS R/

W90P710CD/W90P710CDG - 304 - LCD Timing Control 6 Register (LCDTCON6) REGISTER ADDRESS R/W DESCRIPTION RESET VALUELCDTCON6 0xFFF0_80C4 R LCD

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 305 - Revision B2 Fig. 6.10.3.7.2 TFT Vertical display timing diagram Fig. 6.

W90P710CD/W90P710CDG - 306 - 6.10.3.8 Palette SRAM Build In Self-Test Lookup Table SRAM Build In Self Test Register (BIST) REGISTER ADDRESS R/W

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 307 - Revision B2 6.11 Audio Controller The audio controller consists of IIS/AC-

W90P710CD/W90P710CDG - 308 - LRCLKBCKDATALeft Right123MSBB212LSB M SBI2S busLRCLKBCKDATALeft Right123B2B312MSB B2M S B –Ju stified form atMSBLSBFigu

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 309 - Revision B2 The signal format is shown as Figure 6.11.2.2 Figure

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 31 - Revision B2 Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued)

W90P710CD/W90P710CDG - 310 - Continued. SLOT # BIT DESCRIPTION 19 - 4 PCM playback data for left channel PCM LEFT (slot 3) 3 - 0 This field shoul

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 311 - Revision B2 6.11.3 Audio Controller Register Map R: read only, W: write o

W90P710CD/W90P710CDG - 312 - BITS DESCRIPTIONS [15] Reserved - [14] Reserved - [13] Reserved - [12] R_DMA_IRQ When recording, when the DMA destinat

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 313 - Revision B2 Continued. BITS DESCRIPTIONS [2:1] BLOCK_EN[1:0] Audio interf

W90P710CD/W90P710CDG - 314 - Continued. BITS DESCRIPTIONS [13:12] PLAY_SINGLE [1:0] Playback single/dual channel select bits PLAY_SINGLE[1:0]=11, th

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 315 - Revision B2 BITS DESCRIPTIONS [31:0] AUDIO_RDSTB[31:0] 32-bit record des

W90P710CD/W90P710CDG - 316 - BITS DESCRIPTIONS [31:0] AUDIO_RDST_L[31:0] 32-bit record destination address length The AUDIO_RDST_L[31:0] bits is re

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 317 - Revision B2 BITS DESCRIPTIONS [31:3] Reserved - [2] R_FIFO_FULL Record F

W90P710CD/W90P710CDG - 318 - BITS DESCRIPTIONS [31:0] AUDIO_PDSTB[31:0] 32-bit play destination base address The AUDIO_PDSTB[31:0] bits is read/wri

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 319 - Revision B2 BITS DESCRIPTIONS [31:0] AUDIO_PDST_L[31:0] 32-bit play dest

W90P710CD/W90P710CDG - 32 - Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3Mem

W90P710CD/W90P710CDG - 320 - BITS DESCRIPTIONS [31:3] Reserved - [2] P_FIFO_EMPTY Playback FIFO empty indicator bit P_FIFO_EMPTY=0, the playback FI

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 321 - Revision B2 The ACTL_IISCON is the IIS basic operation control register.

W90P710CD/W90P710CDG - 322 - Continued BITS DESCRIPTIONS [7:6] BCLK_SEL [1:0] IIS serial data clock frequency selection bit BCLK_SEL[1:0]=00, 32fs i

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 323 - Revision B2 BITS DESCRIPTIONS [6] Reserved - [5] AC_BCLK_PU_EN This bit

W90P710CD/W90P710CDG - 324 - Continued. BITS DESCRIPTIONS [2] AC_W_RES AC-link warm reset control bit, when this bit is set to 1, (AC-link begin war

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 325 - Revision B2 BITS DESCRIPTIONS [31:5] Reserved - [4] VALID_FRAME Frame va

W90P710CD/W90P710CDG - 326 - BITS DESCRIPTIONS [31:8] Reserved - [7] R_WB Read/Write select bit R_WB=1, a read specified by R_INDEX[6:0] will occur

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 327 - Revision B2 AC-link input slot 0 (ACTL_ACIS0) REGISTER ADDRESS R/W DESCR

W90P710CD/W90P710CDG - 328 - AC-link input slot 1 (ACTL_ACIS1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_ACIS1 0xFFF0_9040 R AC-link in

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 329 - Revision B2 AC-link input slot 2 (ACTL_ACIS2) REGISTER ADDRESS R/W DESCR

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 33 - Revision B2 6. FUNCTIONAL DESCRIPTION 6.1 ARM7TDMI CPU CORE The ARM7TDMI

W90P710CD/W90P710CDG - 330 - 6.12 Universal Asynchronous Receiver/Transmitter Controller Asynchronous serial communication block include 4 UART bloc

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 331 - Revision B2 Accessory Function : IrDA SIR (optional)

W90P710CD/W90P710CDG - 332 - 6.12.1 UART0 UART0 is a general UART block. It has not Modem I/O signals. More detail function description, please refe

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 333 - Revision B2 Table 6.12.2.1 UART1 Register Map REGISTER ADDRESS R/W OTHER

W90P710CD/W90P710CDG - 334 - BITS DESCRIPTIONS [31:3] Reserved - [2:0] UBCR UBCR is a 3 bits register which is used to select clock source to gener

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 335 - Revision B2 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18

W90P710CD/W90P710CDG - 336 - 6.12.4 UART3 UART3 is a general UART block. It has not Modem I/O signals. More detail general UART function description

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 337 - Revision B2 UART3 Modem Status Register (UART3_MSR) REGISTER ADDRESS R/W D

W90P710CD/W90P710CDG - 338 - y Line break generation and detection y False start bit detection y Full prioritized interrupt system controls y Loo

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 339 - Revision B2 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 1

W90P710CD/W90P710CDG - 34 - 6.2 System Manager 6.2.1 Overview The W90P710 System Manager has the following functions. y System memory map y Data bu

W90P710CD/W90P710CDG - 340 - UART Interrupt Enable Register (UART_IER) REGISTER OFFSET R/W DESCRIPTION RESET VALUEUART_IER 0x04 R/W Interrupt Ena

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 341 - Revision B2 UART Divider Latch (Low Byte) Register (UART_DLL) REGISTER OFF

W90P710CD/W90P710CDG - 342 - This 16-bit divider {DLM, DLL} is used to determine the baud rate as follows Baud Rate = Crystal Clock / {16 * [Div

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 343 - Revision B2 Table 6.12.5.1 Interrupt Control Functions IIR [3:0] PRIORITY

W90P710CD/W90P710CDG - 344 - BITS DESCRIPTIONS [7:6] RFITL RX FIFO Interrupt (Irpt_RDA) Trigger Level RFITL [7:6] Irpt_RDA Trigger Level (Bytes)00

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 345 - Revision B2 BITS DESCRIPTIONS [7] DLAB Divider Latch Access Bit 0 = It i

W90P710CD/W90P710CDG - 346 - UART Modem Control Register (UART_MCR) REGISTER OFFSET R/W DESCRIPTION RESET VALUEUART_MCR 0x10 R/W Modem Control Re

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 347 - Revision B2 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 1

W90P710CD/W90P710CDG - 348 - Continued. BITS DESCRIPTIONS [2] PEI Parity Error Indicator This bit is set to logic 1 whenever the received character

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 349 - Revision B2 BITS DESCRIPTIONS [31:6] Reserved - [5] DSR# Complement vers

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 35 - Revision B2 ROM/FLASH256KB - 16MBSDRAM Bank 02MB - 64MBSDRAM Bank 12MB - 64

W90P710CD/W90P710CDG - 350 - 6.12.6 High speed UART Controller The High Speed Universal Asynchronous Receiver/Transmitter (HS_UART) performs a seria

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 351 - Revision B2 Continued. REGISTER OFFSET R/W DESCRIPTION RESET VALUEHSUA

W90P710CD/W90P710CDG - 352 - HSUART Transmit Holding Register (HSUART_THR) REGISTER OFFSET R/W DESCRIPTION RESET VALUEHSUART_THR 0x00 W Transmi

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 353 - Revision B2 BITS DESCRIPTIONS [31:5] Reserved - [4] nDBGACK_EN ICE debug

W90P710CD/W90P710CDG - 354 - BITS DESCRIPTIONS [31:8] Reserved - [7:0] Baud Rate Divisor (Low Byte) The low byte of the baud rate divider HSUART D

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 355 - Revision B2 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 1

W90P710CD/W90P710CDG - 356 - Interrupt Control Functions IIR [3:0] PRIORITY INTERRUPT TYPE INTERRUPT SOURCE INTERRUPT RESET CONTROL - - - 1 -- No

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 357 - Revision B2 BITS DESCRIPTIONS [31:8] Reserved - [7:4] RFITL RX FIFO Inter

W90P710CD/W90P710CDG - 358 - HSUART Line Control Register (HSUART_LCR) REGISTER OFFSET R/W DESCRIPTION RESET VALUEHSUART_LCR 0x0C R/W Line Con

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 359 - Revision B2 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 1

W90P710CD/W90P710CDG - 36 - Table 6.2.1 On-Chip Peripherals Memory Map BASE ADDRESS DESCRIPTION AHB Peripherals 0xFFF0_0000 Product Identifier Re

W90P710CD/W90P710CDG - 360 - Continued. BITS DESCRIPTIONS [3:2] Reserved - [1] RTS# Complement version of RTS# (Request-To-Send) signal Writing 0x00

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 361 - Revision B2 Continued. BITS DESCRIPTIONS [5] THRE Transmitter Holding Reg

W90P710CD/W90P710CDG - 362 - HSUART Modem Status Register (HSUART_MSR) REGISTER OFFSET R/W DESCRIPTION RESET VALUEHSUART_MSR 0x18 R MODEM Status Re

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 363 - Revision B2 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 1

W90P710CD/W90P710CDG - 364 - 6.13 Timer/Watchdog Controller 6.13.1 General Timer Controller The timer module includes two channels, TIMER0 and TIMER

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 365 - Revision B2 31 30 29 28 27 26 25 24 nDBGACK_EN CEN IE MODE[1:0]

W90P710CD/W90P710CDG - 366 - Continued BITS DESCRIPTIONS [26] CRST Counter Reset Set this bit will reset the TIMER counter, and also force CEN to 0.

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 367 - Revision B2 BITS DESCRIPTIONS [31:24] Reserved Reserved [23:0] TIC Timer

W90P710CD/W90P710CDG - 368 - Timer Interrupt Status Register (TISR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE TISR 0xFFF8_1018 R/W Timer In

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 369 - Revision B2 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 1

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 37 - Revision B2 Table 6.2.1 On-Chip Peripherals Memory Map (Continued) BASE AD

W90P710CD/W90P710CDG - 370 - Continued BITS DESCRIPTIONS [6] WTIE Watchdog Timer Interrupt Enable 0 = Disable the Watchdog timer interrupt 1 = Enabl

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 371 - Revision B2 Continued BITS DESCRIPTIONS [1] WTRE Watchdog Timer Reset Ena

W90P710CD/W90P710CDG - 372 - 6.14 Advanced Interrupt Controller An interrupt temporarily changes the sequence of program execution to react to a pa

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 373 - Revision B2 6.14.1 Interrupt Sources Table 6.14.1 W90P710 Interrupt Sour

W90P710CD/W90P710CDG - 374 - AIC Functional Description Hardware Interrupt Vectoring The hardware interrupt vectoring can be used to shorten the inte

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 375 - Revision B2 Interrupt Masking Each interrupt source, including FIQ, can be

W90P710CD/W90P710CDG - 376 - ACTION NORMAL MODE ICE/DEBUG MODE Calculate active interrupt Read AIC_IPER Read AIC_IPER Determine and return the v

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 377 - Revision B2 AIC Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION

W90P710CD/W90P710CDG - 378 - AIC Source Control Registers (AIC_SCR1 ~ AIC_SCR31) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_SCR1 0xFFF8_2004

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 379 - Revision B2 Continued BITS DESCRIPTIONS [5:3] Reserved Reserved [2:0] PRI

W90P710CD/W90P710CDG - 38 - Big endian In Big endian format, the W90P710 stores the most significant byte of a word at the lowest numbered byte, and

W90P710CD/W90P710CDG - 380 - AIC Interrupt Active Status Register (AIC_IASR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_IASR 0xFFF8_2104 R In

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 381 - Revision B2 31 30 29 28 27 26 25 24 IS31 IS30 IS29 IS28 IS27 IS26

W90P710CD/W90P710CDG - 382 - BITS DESCRIPTIONS [6:2] Vector When the AIC generates the interrupt, VECTOR represents the interrupt channel number tha

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 383 - Revision B2 AIC Interrupt Mask Register (AIC_IMR) REGISTER ADDRESS R/W DE

W90P710CD/W90P710CDG - 384 - The AIC classifies the interrupt into FIQ and IRQ. This register indicates whether the asserted interrupt is FIQ or IRQ.

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 385 - Revision B2 AIC Mask Disable Command Register (AIC_MDCR) REGISTER ADDRESS

W90P710CD/W90P710CDG - 386 - BITS DESCRIPTIONS [31:1] SSCx When the W90P710 is under debugging or verification, software can activate any interrupt

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 387 - Revision B2 AIC End of Service Command Register (AIC_EOSCR) REGISTER ADDRE

W90P710CD/W90P710CDG - 388 - BITS DESCRIPTIONS [31:1] Reserved Reserved [0] TEST This register indicates whether AIC_IPER will be cleared or not af

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 389 - Revision B2 6.15 General-Purpose Input/Output The General-Purpose Input

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 39 - Revision B2 Fig6.2.5 CPU registers Read/Write with external memory Table 6

W90P710CD/W90P710CDG - 390 - Table 6.16.1 GPIO multiplexed functions table, continued 6 GPIO26 SC0_PRES SD_DAT1 VD14 7 GPIO27 SC0_RST SD_DAT0 VD

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 391 - Revision B2 Table 6.16.1 GPIO multiplexed functions table, continued 7 GPI

W90P710CD/W90P710CDG - 392 - 6.15.1 GPIO Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG0 0xFFF8_3000 R/W GPIO port0

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 393 - Revision B2 GPIO Control Registers Map, continued REGISTER ADDRESS R/W DES

W90P710CD/W90P710CDG - 394 - 11 10 01 00 PT0CFG0 Name Type Name Type Name Type Name TypePORT00 USB_PWREN O nIRQ4 AC97RESETor I2SMCLK O GPIO0 I/O

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 395 - Revision B2 31 30 29 28 27 26 25 24 RESERVED 23 22 21 20 19 18

W90P710CD/W90P710CDG - 396 - 31 30 29 28 27 26 25 24 RESERVED 23 22 21 20 19 18 17 16 RESERVED 15 14 13 12 11 10 9 8 RESERVED 7

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 397 - Revision B2 GPIO Port1 Configuration Register (GPIO_CFG1) REGISTER ADDRESS

W90P710CD/W90P710CDG - 398 - 11 10 01 00 PT1CFG5 Name Type Name Type Name Type Name TypePORT1_5 VD13 SC0_PWR O SD_DAT2 I/O GPIO25 I/O 11 10 01 0

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 399 - Revision B2 BITS DESCRIPTION [31:26] RESERVED - [25:16] PUPEN1 GPIO51 ~

W90P710CD/W90P710CDG - 4 - 6.8.1 USB Endpoints ...

W90P710CD/W90P710CDG - 40 - Table6.2.4 Word access read operation with Big Endian ACCESS OPERATION READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY) X

W90P710CD/W90P710CDG - 400 - GPIO Port1 Data Input Register (GPIO_DATAIN1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUEGPIO_DATAIN1 0xFFF8_301C R/W

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 401 - Revision B2 *In the following pin definition, mark with shading is default

W90P710CD/W90P710CDG - 402 - 11 10 01 00 PT2CFG9 Name Type Name Type Name Type Name TypePORT2_9 VD17 O KPROW1 O PHY_MDC O GPIO51 I/O GPIO Port2 D

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 403 - Revision B2 PGPIO Port2 Data Output Register (GPIO_DATAOUT2) REGISTER ADDR

W90P710CD/W90P710CDG - 404 - BITS DESCRIPTION [31:10] RESERVED - [9:0] DATAIN2 Port2 input data register The DATAIN2 indicates the status of each

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 405 - Revision B2 11 10 01 00 PT3CFG3 Name Type Name TypeName Type Name TypeP

W90P710CD/W90P710CDG - 406 - BITS DESCRIPTION [31:24] RESERVED - [23:16] PUPEN2 After power on, the registers are disabled. [15:8] RESERVED GPIO67 ~

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 407 - Revision B2 GPIO Port3 Data Input Register (GPIO_DATAIN3) REGISTER ADDRESS

W90P710CD/W90P710CDG - 408 - *In the following pin definition, mark with shading is default function. 11 10 01 00 PT4CFG0 Name Type Name TypeName Ty

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 409 - Revision B2 11 10 01 00 PT4CFG8 Name Type Name Type Name Type Name Type

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 41 - Revision B2 Table6.2.6 Half-word access read operation with Big Endian ACCE

W90P710CD/W90P710CDG - 410 - Continued BITS DESCRIPTION [10:0] OMDEN4 GPIO70~GPIO68 and GPIO59~GPIO52 output mode enable 1 = enable 0 = disable NO

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 411 - Revision B2 31 30 29 28 27 26 25 24 RESERVED 23 22 21 20 19 1

W90P710CD/W90P710CDG - 412 - 11 10 01 00 PT5CFG1 Name Type Name Type Name TypeName TypePORT5_1 RESERVED RESERVED RXD0 I GPIO6 I/O 11 10 01 00 P

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 413 - Revision B2 11 10 01 00 PT5CFG9 Name Type Name Type Name TypeName TypePO

W90P710CD/W90P710CDG - 414 - 31 30 29 28 27 26 25 24 RESERVED PUPEN5[14:8] 23 22 21 20 19 18 17 16 PUPEN5[7:0] 15 14 13 12 11 10

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 415 - Revision B2 BITS DESCRIPTION [31:15] RESERVED - [14:0] DATAOUT5 PORT5 da

W90P710CD/W90P710CDG - 416 - 31 30 29 28 27 26 25 24 RESERVED 23 22 21 20 19 18 17 16 PT6CFG11 PT6CFG10 PT6CFG9 PT6CFG8 15 14 13

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 417 - Revision B2 11 10 01 00 PT6CFG5 Name Type Name Type Name Type Name Type

W90P710CD/W90P710CDG - 418 - 31 30 29 28 27 26 25 24 RESERVED PUPEN6[11:8] 23 22 21 20 19 18 17 16 PUPEN6[7:0] 15 14 13 12 11 10

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 419 - Revision B2 BITS DESCRIPTION [31:12] RESERVED - [11:0] DATAOUT6 PORT6 dat

W90P710CD/W90P710CDG - 42 - Table6.2.7 Byte access write operation with Big Endian ACCESS OPERATION WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)

W90P710CD/W90P710CDG - 420 - 31 30 29 28 27 26 25 24 RESERVED 23 22 21 20 19 18 17 16 RESERVED 15 14 13 12 11 10 9 8 RESERVED 7

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 421 - Revision B2 31 30 29 28 27 26 25 24 RESERVED 23 22 21 20 19 1

W90P710CD/W90P710CDG - 422 - Continued BITS DESCRIPTION [3] EnINT4 Enable INT4 Setting this bit 1 to enable extend interrupt 4 1 = Enable interrup

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 423 - Revision B2 BITS DESCRIPTION [31:2] RESERVED - [1] INT5 Interrupt 5 stat

W90P710CD/W90P710CDG - 424 - 6.16 Real Time Clock Real Time Clock (RTC) block can be operated by independent power supply while the system power is

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 425 - Revision B2 Tick Time interrupt: RTC block use a counter to calibrate the

W90P710CD/W90P710CDG - 426 - 6.16.1 RTC Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_INIR 0xFFF8_4000 R/W RTC Initiation Reg

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 427 - Revision B2 BITS DESCRIPTIONS [31:0] INIR INIR [31:0]: The INIR register

W90P710CD/W90P710CDG - 428 - RTC Frequency Compensation Register (RTC_FCR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_FCR 0xFFF8_4008 R/W

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 429 - Revision B2 Continued BITS DESCRIPTIONS Example 1 Frequency counter measu

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 43 - Revision B2 Table 6.2.9 and Table 6.2.10 Using little-endian and word acces

W90P710CD/W90P710CDG - 430 - RTC Calendar Loading Register (RTC_CLR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_CLR 0xFFF8_4010 R/W RTC Ca

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 431 - Revision B2 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 1

W90P710CD/W90P710CDG - 432 - RTC Day of the Week Register (RTC_DWR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_DWR 0xFFF8_4018 R/W Day of

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 433 - Revision B2 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 1

W90P710CD/W90P710CDG - 434 - 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Hi_year_alarm Lo_year_alarm 15 14 13 12 11

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 435 - Revision B2 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 1

W90P710CD/W90P710CDG - 436 - BITS DESCRIPTIONS [31:2] Reserved - [1] Tick_int_en 1 = RTC Time Tick Interrupt and counter enable 0 = RTC Time Tick I

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 437 - Revision B2 Continued BITS DESCRIPTIONS [0] Alarm_int_st RTC Alarm Interr

W90P710CD/W90P710CDG - 438 - BITS DESCRIPTIONS [31:3] Reserved - [2:0] TTI RTC Tick Time Interrupt request Interval The TTR [2:0] is used to selec

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 439 - Revision B2 6.16.2 RTC Application Note Detect RTC frequency Step1. Conf

W90P710CD/W90P710CDG - 44 - Table 6.2.11 and Table 6.2.12 Using little-endian and half-word access, Program/Data path between register and external m

W90P710CD/W90P710CDG - 440 - 6.17 Smart Card Host Interface The Smart Card resides in APB bus. The whole chip of W90P710 operates at voltage level o

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 441 - Revision B2 Table 6.12.2.1 Smart Card Host Interface 0 Register Map, conti

W90P710CD/W90P710CDG - 442 - 6.17.2 Register Description Receive Buffer Register (SCHI_RBR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUESCHI_RBR0

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 443 - Revision B2 BITS DESCRIPTIONS [31:8] RESERVED - [7:0] TxBDATA 8-bit Tr

W90P710CD/W90P710CDG - 444 - BITS DESCRIPTIONS [31:11] RESERVED - [10] ETOR2 TOR2 interrupt enable bit When 24 bit time-out counter decrease to

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 445 - Revision B2 Continued BITS DESCRIPTIONS [1] ETBREI Enable Transmit Buffe

W90P710CD/W90P710CDG - 446 - BITS DESCRIPTIONS [31:6] RESERVED - [5] SCPSNT Smart card present line status. User may poll this bit to see SCPSNT

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 447 - Revision B2 Smart Card FIFO control Register (SCHI_SCFR) REGISTER ADDRESS

W90P710CD/W90P710CDG - 448 - Continued BITS DESCRIPTIONS [5:3] PEC2, PEC1, PEC0 Parity Error Count. Bits PEC2, PEC1 and PEC0 determine the number o

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 449 - Revision B2 BITS DESCRIPTIONS [31:8] RESERVED - [7] BDLAB Baud rate Div

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 45 - Revision B2 Table 6.2.13 and Table 6.2.14 Using little-endian and byte acce

W90P710CD/W90P710CDG - 450 - Contiuned BITS DESCRIPTIONS [2] CDP Card Detect Polarity. We can use the CDP bit to choose the card present input polar

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 451 - Revision B2 Smart Card Host Status Register (SCHI_SCSR) REGISTER ADDRESS R

W90P710CD/W90P710CDG - 452 - Contiuned BITS DESCRIPTIONS [5] TBRE Transmitter Buffer Register Empty In non-FIFO mode, this bit will be set to a log

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 453 - Revision B2 BITS DESCRIPTIONS [31:8] RESERVED - [7:0] GTR Guard Time

W90P710CD/W90P710CDG - 454 - BITS DESCRIPTIONS [31:11] RESERVED - [10:8] PSCKFS2, PSCKFS1, PSCKFS0 PSCK Frequency Selection bit 2, 1 and 0. This

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 455 - Revision B2 Smart Card Host Test Mode Register (SCHI_TMR) REGISTER ADDRESS

W90P710CD/W90P710CDG - 456 - BITS DESCRIPTIONS [31:2] RESERVED - [1] SCRST_L Smart card Reset pin control bit Software driver controls this bit d

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 457 - Revision B2 BITS DESCRIPTIONS [31:12] RESERVED - [11] nDBGACK_EN2 ICE D

W90P710CD/W90P710CDG - 458 - Continued BITS DESCRIPTIONS [10:8] TOC8, TOC7, TOC6 TOC8, TOC7, TOC6 (Time Out Configuration) control 24 bit time-out

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 459 - Revision B2 Continued BITS DESCRIPTIONS [6:4] TOC5, TOC4, TOC3 TOC5, TOC

W90P710CD/W90P710CDG - 46 - 6.2.5 Bus Arbitration The W90P710’s internal function blocks or external devices can request mastership of the system bus

W90P710CD/W90P710CDG - 460 - Continued BITS DESCRIPTIONS [2:0] TOC2, TOC1, TOC0 TOC5, TOC4, TOC3 (Time Out Configuration) control 8 bit time-out cou

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 461 - Revision B2 Smart Card Host Time-out Initial Register 0 (SCHI_TOIR 0) REGI

W90P710CD/W90P710CDG - 462 - BITS DESCRIPTIONS [31:16] RESERVED - [15:0] TOIR1 16 bit Time Out Initial Register 1 The value to load in register T

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 463 - Revision B2 Smart Card Host Time-Out Data Register 0 (SCHI_TODR0) REGISTER

W90P710CD/W90P710CDG - 464 - BITS DESCRIPTIONS [31:16] RESERVED - [15:0] TOD1 16 bit Time Out Data count Register 1 The value showing in register

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 465 - Revision B2 Smart Card Host Buffer Time-Out Data Register (SCHI_BTOR) REGI

W90P710CD/W90P710CDG - 466 - BITS DESCRIPTIONS [31:8] RESERVED - [7:0] BLL 8 bit Baud rate divider Latch Low byte register This register combinin

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 467 - Revision B2 BITS DESCRIPTIONS [31:8] RESERVED - [7:0] BLH 8 bit Baud

W90P710CD/W90P710CDG - 468 - 6.17.3 Functional description The following description uses abbreviations to refer to control/status registers and thei

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 469 - Revision B2 convention is for inserted card and chooses a conversion proce

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 47 - Revision B2 6.2.5.2 Rotate Priority Mode In Rotate Priority Mode (PRTMOD=1

W90P710CD/W90P710CDG - 470 - These I/O conditions also apply to socket in power down state (SCPWD = 1) or deselected socket in idle state. Designers

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 471 - Revision B2 6.18 I2C Interface I2C is a two-wire, bi-directional serial bu

W90P710CD/W90P710CDG - 472 - 6.18.1 I2C Protocol Normally, a standard communication consists of four parts: 1) START or Repeated START signal genera

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 473 - Revision B2 START or Repeated START signal When the bus is free/idle, mean

W90P710CD/W90P710CDG - 474 - Data Transfer Once successful slave addressing has been achieved, the data transfer can proceed on a byte-by-byte basis

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 475 - Revision B2 6.18.2 I2C Serial Interface Control Registers Map R: read on

W90P710CD/W90P710CDG - 476 - BITS DESCRIPTIONS [31:12] Reserved Reserved [11] I2C_RxACK Received Acknowledge From Slave (Read only) This flag repre

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 477 - Revision B2 I2C Prescale Register 0/1 (I2C_DIVIDER 0 /1) REGISTER ADDRESS

W90P710CD/W90P710CDG - 478 - 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 479 - Revision B2 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 1

W90P710CD/W90P710CDG - 48 - FOUT(PLL)HCLKidle_stateMCLK(ARM)HCLK(cache)IDLE PeriodHCLK(memc)Case1. IDLE=1, PD=0, MIDLE=0 Fig. 6.2.7 Clock management

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 481 - Revision B2 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 1

W90P710CD/W90P710CDG - 482 - BITS DESCRIPTIONS [31:0] Tx Data Transmit Register The I2C core used 32-bit transmit buffer and provide multi-byte tra

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 483 - Revision B2 6.19 Universal Serial Interface The USI is a synchronous seri

W90P710CD/W90P710CDG - 484 - mw_ss_omw_sclk_omw_so_omw_si_iCNTRL[LSB]=1, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08,CNTRL[Tx_NEG]=0, CNTRL[Rx_NEG]=1,

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 485 - Revision B2 USI_Control and Status Register (USI_CNTRL) REGISTER ADDRESS R

W90P710CD/W90P710CDG - 486 - Continued BITS DESCRIPTIONS [11] Reserved Reserved [10] LSB Send LSB First 0 = The MSB is transmitted/received first (w

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 487 - Revision B2 USI Divider Register (USI_DIVIDER) REGISTER ADDRESS R/W DESCR

W90P710CD/W90P710CDG - 488 - 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 489 - Revision B2 USI Data Receive Register 0/1/2/3 (USI_Rx0/1/2/3) REGISTER ADD

W90P710CD/W90P710CDG - 490 - 31 30 29 28 27 26 25 24 Tx [31:24] 23 22 21 20 19 18 17 16 Tx [23:16] 15 14 13 12 11 10 9 8 Tx [15:

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 49 - Revision B2 HCLK(cache)Case3. IDLE=0, PD=1, MIDLE=0EXTALidle _statepd_state

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 491 - Revision B2 6.20 PWM The W90P710 have 4 channels PWM timers. They can be d

W90P710CD/W90P710CDG - 492 - The auto-reload operation copies from PWM_CNR0, PWM_CNR1, PWM_CNR2, PWM_CNR3 to down-counter when down-counter reaches z

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 493 - Revision B2 Dead zone generator operationPWM_out1PWM_out1_nPWM_out1_DZPWM_

W90P710CD/W90P710CDG - 494 - 6.20.6 PWM Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_PPR 0xFFF8_7000 R/W PWM Prescaler Register

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 495 - Revision B2 BITS DESCRIPTIONS [31:24] DZI1 DZI1: Dead zone interval regi

W90P710CD/W90P710CDG - 496 - CSR3 INPUT CLOCK DIVIDED BY 000 2 001 4 010 8 011 16 100 1 PWM Control Register (PWM_PCR) REGISTER ADDRESS R/W DESCRI

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 497 - Revision B2 Continued BITS DESCRIPTIONS [15] PCR 15 Channel 2 toggle/one

W90P710CD/W90P710CDG - 498 - Continued BITS DESCRIPTIONS [03] PCR 03 Channel 0 toggle/one shot mode 1 = toggle mode 0 = one shot mode [02] PCR 02 Ch

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 499 - Revision B2 BITS DESCRIPTIONS [31:16] Reserved - [15:0] CNRx CNR: PWM co

W90P710CD/W90P710CDG - 500 - PWM Data Register 0/1/2/3 (PWM_PDR 0/1/2/3) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_PDR0 0xFFF8_7014 R PWM D

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 5 - Revision B2 6.19 Universal Serial Interface...

W90P710CD/W90P710CDG - 50 - 6.2.8 System Manager Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUEPDID 0xFFF0_0000 R Product Iden

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 501 - Revision B2 BITS DESCRIPTIONS [31:4] Reserved - [3] PIER3 Enable/Disable

W90P710CD/W90P710CDG - 502 - 6.21 Keypad Interface W90P710 Keypad Interface (KPI) is an APB slave with 4-row scan output and 8-column scan input. KPI

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 503 - Revision B2 W90P7104 :16DECODERROW[[16:0]KPIC[7:0]KPIR[3:0]COL[7:0]16x8key

W90P710CD/W90P710CDG - 504 - 6.21.2 Register Description Keypad Controller Configuration Register (KPI_CONF) REGISTER ADDRESS R/W DESCRIPTION RESET

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 505 - Revision B2 Continued BITS DESCRIPTION [18] ENKP Key pad scan enable Sett

W90P710CD/W90P710CDG - 506 - COL[0]COL[1]COL[2]COL[3]A0A1A2GS16x8 keys matrixROW[15:0]COL[7:0]IN[7:0]74148ENCODER74138ROW[3:0]W90P710keypad I/F with

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 507 - Revision B2 BITS DESCRIPTION [31:26] RESERVED - [25] EN3KY Enable three-

W90P710CD/W90P710CDG - 508 - KeyPad Interface Low Power Mode Configuration Register (KPILPCONF) REGISTER ADDRESS R/W DESCRIPTION RESET VALUEKPILPCOF

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 509 - Revision B2 Key Pad Interface Status Register (KPISTATUS) REGISTER ADDRESS

W90P710CD/W90P710CDG - 510 - Continued BITS DESCRIPTION [17] 2KEY Double-key press This bit indicates that 2 keys have been detected. Software can r

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 51 - Revision B2 BITS DESCRIPTION [31:30] PACKAGE Package Type Select These tw

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 511 - Revision B2 6.22 PS2 Host Interface Controller W90P710 PS2 host controlle

W90P710CD/W90P710CDG - 512 - 6.22.1 PS2 Host Controller Interface Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUEPS2CMD 0xFFF8_9000

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 513 - Revision B2 Continued BITS DESCRIPTIONS [8] EnCMD Enable write PS2 Host C

W90P710CD/W90P710CDG - 514 - Continued BITS DESCRIPTIONS [3:1] Reserved [0] RX_IRQ This Receive Interrupt bit indicates software that Host control

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 515 - Revision B2 Continued BITS DESCRIPTIONS [8] RX_extend Receive Extend Byte

W90P710CD/W90P710CDG - 516 - 7. ELECTRICAL SPECIFICATIONS 7.1 Absolute Maximum Ratings Ambient temperature ...…………….

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 517 - Revision B2 Table 7.2.1TSMC IO DC Characteristics PARAMETER MIN. TYP. M

W90P710CD/W90P710CDG - 518 - 7.2.2 USB Transceiver DC Characteristics SYMBOL PARAMETER CONDITIONS MIN. MAX. UNITVDI Differential Input Sensiti

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 519 - Revision B2 7.3.2 EBI/(ROM/SRAM/External I/O) AC Characteristics Address

W90P710CD/W90P710CDG - 520 - 7.3.3 USB Transceiver AC Characteristics Low Speed: 75ns at CL = 50pF, 300ns at CL = 350pFFull Speed: 4 to 20ns at C

W90P710CD/W90P710CDG - 52 - PLL Control Register0 （PLLCON0） W90P710 provides two clock generation options – crystal and oscillator. The external clo

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 521 - Revision B2 7.3.4 EMC RMII AC Characteristics The signal timing character

W90P710CD/W90P710CDG - 522 - PHY_MDCPHY_MDIO (Write)TMDOvalid dataTMDHvalid dataTMDSTMDHPHY_MDIO(Read) SYMBOL DESCRIPTION MIN MAX UNIT TMDO MDIO O

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 523 - Revision B2 7.3.5 LCD Interface AC Characteristics THOLDTDELAYVCLKVSYNCH

W90P710CD/W90P710CDG - 524 - 7.3.6 SD Interface AC Characteristics TwhTppTwlTisuTihTod(max)TohSD_CLKSD_CMDSD_DAT(Input)SD_CMDSD_DAT(Output) SYMBOL

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 525 - Revision B2 7.3.7 AC97/I2S Interface AC Characteristics TISUTODTIHDTOHAC9

W90P710CD/W90P710CDG - 526 - TDISTDIHTDOHTout_delayTBCLK_PERIODI2S_BCLKI2S_DATAOI2S_RLCLKI2S_DATAI SYMBOLS DESCRIPTION MIN MAX UNIT TBCLK_PERIOD IIS

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 527 - Revision B2 7.3.8 Smart Card Interface AC Characteristics Tclk_datTclkhT

W90P710CD/W90P710CDG - 528 - 7.3.9 I2C Interface AC Characteristics TSU:STOTSU:DAT2TLOWTHIGHThd:DATTSU:DATThd:STASCLSDA SCLSDATSU:SAT

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 529 - Revision B2 SYMBOL DESCRIPTION MIN MAX UNIT THIGH I2C Clock high time 1

W90P710CD/W90P710CDG - 530 - FUSITleadTCLKHTCLKLTISUTISUTIHTIHTlagSFRMSCLKSSPRXD(RX_NEG =1)SSPRXD(RX_NEG =0) SYMBOL DESCRIPTION MIN MAX UNIT FUSI USI

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 53 - Revision B2 Input Divider(NR)PFDFeedbackDivider(NF)ChargePumpVCOOutputDivid

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 531 - Revision B2 7.3.11 PS2 Interface AC Characteristics PS2_CLKPS2_DATAT1T2T3

W90P710CD/W90P710CDG - 532 - 8. ORDERING INFORMATION PART NUMBER NAME PACKAGE DESCRIPTION W90P710CD LQFP176 176 Leads, body 22 x 22 x 1.4 mm W90

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 533 - Revision B2 9. PACKAGE SPECIFICATIONS 176L LQFP (20X20X1.4 mm footprint 2

W90P710CD/W90P710CDG - 534 - 10. APPENDIX A: W90P710 REGISTERS MAPPING TABLE R: read only, W: write only, R/W: both read and write, C: Only value 0 c

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 535 - Revision B2 Cache Control Registers Map REGISTER ADDRESS R/W DESCRIPTIO

W90P710CD/W90P710CDG - 536 - EMC Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUECAM12M 0xFFF0_3068 R/W CAM12 Most Signi

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 537 - Revision B2 EMC Registers Map, continued REGISTER ADDRESS R/W DESCRIPTI

W90P710CD/W90P710CDG - 538 - USB Host Controller Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE OpenHCI Registers HcRevision 0xFFF0_5000

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 539 - Revision B2 USB Device Register Map REGISTER OFFSET R/W DESCRIPTION RESE

W90P710CD/W90P710CDG - 540 - USB Device Register Map, continued REGISTER OFFSET R/W DESCRIPTION RESET VALUE EPC_INFO 0xFFF0_6080 R/W USB endpoint

W90P710CD/W90P710CDG - 54 - BITS DESCRIPTION [31:29] RESERVED - [28] PS2 PS2 controller clock enable bit 0 = Disable PS2 controller clock 1 = Enable

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 541 - Revision B2 SD Control Register Map, continued REGISTER OFFSET R/W DESC

W90P710CD/W90P710CDG - 542 - LCDC Control Register Map, continued. REGISTER ADDRESS R/W DESCRIPTION RESET VALUEColor Generation VDLUTENTRY1 0xFFF

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 543 - Revision B2 LCDC Control Register Map, continued. REGISTER ADDRESS R/W D

W90P710CD/W90P710CDG - 544 - UART0 Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUEUART0_RBR 0xFFF8_0000 R Receive Buffer Regi

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 545 - Revision B2 UART2 Control Register Map REGISTER ADDRESS R/W DESCRIPTION

W90P710CD/W90P710CDG - 546 - Timer Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUETCR0 0xFFF8_1000 R/W Timer Control Regist

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 547 - Revision B2 AIC Control Registers Map, continued REGISTER ADDRESS R/W DES

W90P710CD/W90P710CDG - 548 - GPIO Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUEGPIO_CFG0 0xFFF8_3000 R/W GPIO port0 configuratio

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 549 - Revision B2 RTC Control Register Map REGISTER ADDRESS R/W DESCRIPTION

W90P710CD/W90P710CDG - 550 - Smart card Host Control Register Map, continued. REGISTER ADDRESS R/W DESCRIPTION RESET VALUESmartcard Host Interface

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 55 - Revision B2 Continued. BITS DESCRIPTION [17] PWM PWM controller clock enab

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 551 - Revision B2 I2C Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE

W90P710CD/W90P710CDG - 552 - PWM Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_PPR 0xFFF8_7000 R/W PWM Prescaler Regist

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 553 - Revision B2 Important Notice Winbond products are not designed, intende

W90P710CD/W90P710CDG - 56 - Continued. BITS DESCRIPTION [5] UART0 UART0 controller clock enable bit 0 = Disable UART0 controller clock 1 = Enable UA

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 57 - Revision B2 PLL Control Register 1（PLLCON1） W90P710 provides extra PLL for

W90P710CD/W90P710CDG - 58 - Input Divider(NR)PFDFeedbackDivider(NF)ChargePumpVCOOutputDivider(NO)EXTALOTDV1[1:0]PLL1INDV1[4:0]FBDV1[8:0]480MHzFINFOUT

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 59 - Revision B2 IIS Clock Control Register (I2SCKCON) REGISTER ADDRESS R/W DE

W90P710CD/W90P710CDG - 6 - 1. GENERAL DESCRIPTION The W90P710 is built around an outstanding CPU core, the 16/32 ARM7TDMI RISC processor which design

W90P710CD/W90P710CDG - 60 - BITS DESCRIPTION [31:8] RESERVED [7] IRQWAKEUPPOL[3] nIRQ3 wake up polarity 1 = nIRQ3 is high level wake up 0 = nIRQ3

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 61 - Revision B2 31 30 29 28 27 26 25 24 RESERVED 23 22 21 20 19 18

W90P710CD/W90P710CDG - 62 - BITS DESCRIPTION [31:3] RESERVED [2] MIDLE Memory controller IDLE enable Setting both MIDLE and IDLE bits HIGH will le

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 63 - Revision B2 BITS DESCRIPTION [31:1] RESERVED - [0] USBHnD USBHnD[0]: USB t

W90P710CD/W90P710CDG - 64 - 6.3 External Bus Interface 6.3.1 EBI Overview W90P710 supports External Bus Interface (EBI), which controls the access t

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 65 - Revision B2 6.3.2.1 SDRAM Components Supported Table 6.3.2.1 SDRAM support

W90P710CD/W90P710CDG - 66 - SDRAM Data Bus Width: 16-bit Total Type R x C R/C A14 (BS1) A13 (BS0)A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A016M 2Mx

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 67 - Revision B2 SDRAM Data Bus Width: 8-bit Total Type R x C R/C A14 (BS1) A

W90P710CD/W90P710CDG - 68 - 6.3.2.3 SDRAM Interface MCLKMCKEnSCS[1:0]nSRASnSCASnSWEnSDQM[3:0]A[21:0]D[31:0]A[10:0]DQ[[31:0]DQM[3:0]nWEnCASnRASnCSBS0B

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 69 - Revision B2 EBI Control Register (EBICON) REGISTER ADDRESS R/W DESCRIPTION

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 7 - Revision B2 Ethernet MAC Controller y DMA engine with burst mode y MAC Tx/

W90P710CD/W90P710CDG - 70 - Continued. BITS DESCRIPTION [24] EXBE0 External IO bank 0 byte enable This bit function description is the same as EXBE3

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 71 - Revision B2 Continued. BITS DESCRIPTION [2:1] WAITVT Valid time of nWAIT s

W90P710CD/W90P710CDG - 72 - BITS DESCRIPTION [31:19] BASADDR Base address pointer of ROM/Flash bank The start address is calculated as ROM/Flash ba

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 73 - Revision B2 Continued. BITS DESCRIPTION [3:2] BTSIZE Boot ROM/FLASH data b

W90P710CD/W90P710CDG - 74 - Fig 6.3.3 ROM/FLASH Page Read Operation Timing Configuration Registers（SDCONF0/1） The configuration registers enable soft

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 75 - Revision B2 BITS DESCRIPTION [31:19] BASADDR Base address pointer of SDRA

W90P710CD/W90P710CDG - 76 - Continued. BITS DESCRIPTION [4:3] COLUMN Number of column address bits in SDRAM bank 0/1 Indicates the number of column

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 77 - Revision B2 31 30 29 28 27 26 25 24 RESERVED 23 22 21 20 19 18

W90P710CD/W90P710CDG - 78 - Continued. BITS DESCRIPTION [2:0] tRAS SDRAM bank 0/1, Row active time tRAS [2:0] MCLK 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 79 - Revision B2 External I/O Control Registers（EXT0CON – EXT3CON） The W90P710

W90P710CD/W90P710CDG - 8 - (5) LCD Post processing y Support for one OSD (On-Screen-Display) overlay y Support various OSD function y Programmabl

W90P710CD/W90P710CDG - 80 - Continued. BITS DESCRIPTION [15] ADRS Address bus alignment for external I/O bank 0~3 When ADRS is set, external addre

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 81 - Revision B2 Continued. BITS DESCRIPTION [7:5] tACS Address set-up before n

W90P710CD/W90P710CDG - 82 - Fig 6.3.6 External I/O write operation timing Fig 6.3.7 External I/O read operation timing

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 83 - Revision B2 A[21:0]D[31:0]nWBE_SDQM[1]nECSnnWEA[21:0]DQ[15:0]nOEnCSnWEnOEnU

W90P710CD/W90P710CDG - 84 - BITS DESCRIPTION [31:16] DLH_CLK_REF Latch DLH_CLK clock tree by HCLK positive edge The SDRAM MCLK is generated by inse

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 85 - Revision B2 Continued. BITS DESCRIPTION [3:0] MCLK_O_D MCLK output delay a

W90P710CD/W90P710CDG - 86 - 6.4 Cache Controller The W90P710 incorporates a 4KB Instruction cache, 4KB Data cache and 8 words write buffer. The I-

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 87 - Revision B2 6.4.3 Instruction Cache The Instruction cache (I-cache) is a 4K

W90P710CD/W90P710CDG - 88 - Instruction Cache Load and Lock The W90P710 supports a cache-locking feature that can be used to lock critical sections

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 89 - Revision B2 6.4.4 Data Cache The W90P710 data cache (D-Cache) is a 4KB two-

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 9 - Revision B2 Advanced Interrupt Controller y 31 interrupt sources, including

W90P710CD/W90P710CDG - 90 - Write Hit：Data is written into both the cache and write buffer. The processor then continues to access the cache, while t

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 91 - Revision B2 The unlock all operation is used to unlock the whole D-Cache. T

W90P710CD/W90P710CDG - 92 - 31 30 29 28 27 26 25 24 RESERVED 23 22 21 20 19 18 17 16 RESERVED 15 14 13 12 11 10 9 8 RESERVED 7

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 93 - Revision B2 REGISTER ADDRESS R/W DESCRIPTION RESET VALUECAHCON 0xFFF0_200

W90P710CD/W90P710CDG - 94 - NOTE：When using the FLHA or ULKA command, you can set both ICAH and DCAH bits to execute entire I-Cache and D-Cache flush

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 95 - Revision B2 Cache Test Register 0 (CTEST0) Cache test control register that

W90P710CD/W90P710CDG - 96 - Cache Test Register 1 (CTEST1) Cache Test Register that will be read back to provide the status of cache RAM BIST. Wheth

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 97 - Revision B2 Continued. BITS DESCRIPTION [2] BFAIL2 BIST test fail for data

W90P710CD/W90P710CDG - 98 - 6.5.1 EMC Functional Description MII Management State Machine The MII management function of EMC is compliant to IEEE 80

W90P710CD/W90P710CDG Publication Release Date: September 19, 2006 - 99 - Revision B2 EMC Descriptors A link-list data structure named as descriptor