
W90P710CD/W90P710CDG
- 354 -
BITS DESCRIPTIONS
[31:8]
Reserved
-
[7:0]
Baud Rate Divisor
(Low Byte)
The low byte of the baud rate divider
HSUART Divisor Latch (High Byte) Register (HSUART_DLM)
REGISTER OFFSET R/W DESCRIPTION RESET VALUE
HSUART_DLM
0x04 R/W Divisor Latch Register (MS) (DLAB = 1) 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Baud Rate Divider (High Byte)
BITS DESCRIPTIONS
[31:8]
Reserved
[7:0]
Baud Rate Divisor
(High Byte)
The high byte of the baud rate divider
This 16-bit divider {DLM, DLL} is used to determine the baud rate as follows
Baud Rate = Crystal Clock / {16 * [Divisor + 2]}
HSUART Interrupt Identification Register (HSUART_IIR)
REGISTER OFFSET R/W DESCRIPTION RESET VALUE
HSUART_IIR
0x08 R Interrupt Identification Register 0x8181_8181
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