Rainbow-electronics W90P710CDG Manual do Utilizador descarregar pdf (Página 177)

100

101

W90P710CD/W90P710CDG

Publication Release Date: September 19, 2006

- 177 - Revision B2

Host Controller Interrupt Status Register

All bits are set by hardware and cleared by software.

RESET

VALUE

HcInterruptStatus 0xFFF0_500C

R/W Host Controller Interrupt Status Register 0x0000_0000

31 30 29 28 27 26 25 24

Reserved OCH Reserved

23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8

Reserved

7 6 5 4 3 2 1 0

Reserved RHSC FNO URE RDT SOF WDH SCO

BITS DESCRIPTION

[31] Reserved

Reserved

[30] OCH

OwnershipChange

This bit is set when the OwnershipChangeRequest bit of

HcCommandStatus is set.

[29:7] Reserved

[6] RHSC

RootHubStatusChange

This bit is set when the content of HcRhStatus or the content of any

HcRhPortStatus register has changed.

[5] FNO

FrameNumberOverflow

Set when bit 15 of FrameNumber changes value.

[4] URE

UnrecoverableError

This event is not implemented and is hard-coded to ‘0.’ Writes are

ignored.

[3] RDT

ResumeDetected

Set when Host Controller detects resume signaling on a downstream

port.

[2] SOF

StartOfFrame

Set when the Frame Management block signals a ‘Start of Frame’

event.

1 2 ... 172 173 174 175 176 177 178 179 180 181 182 ... 551 552

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