
W90P710CD/W90P710CDG
- 176 -
Host Controller Command Status Register
REGISTER ADDRESS R/W DESCRIPTION
RESET
VALUE
HcCommandStatus 0xFFF0_5008
R/W Host Controller Command Status Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved OCR BLF CLF HCR
BITS DESCRIPTION
[31:18] Reserved
Reserved
[17:16] SOC
ScheduleOverrunCount
This field is increment every time the SchedulingOverrun bit in
HcInterruptStatus is set. The count wraps from ‘11’ to ‘00.’
[15:4] Reserved
Reserved. Read/Write 0's
[3] OCR
OwnershipChangeRequest
When set by software, this bit sets the OwnershipChange field in
HcInterruptStatus. The bit is cleared by software.
[2] BLF
BulkListFilled
Set to indicate there is an active ED on the Bulk List. The bit may be
set by either software or the Host Controller and cleared by the Host
Controller each time it begins processing the head of the Bulk List.
[1] CLF
ControlListFilled
Set to indicate there is an active ED on the Control List. It may be set
by either software or the Host Controller and cleared by the Host
Controller each time it begins processing the head of the Control List.
[0] HCR
HostControllerReset
This bit is set to initiate the software reset. This bit is cleared by the
Host Controller, upon completed of the reset operation.
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