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MAXQ3108

Low-Power, Dual-Core Microcontroller

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Detailed Description

The MAXQ3108 microcontroller is an integrated, low-

cost solution to simplify the design of electricity meter-

ing and industrial control products. Standard features

include two highly optimized, single-cycle, MAXQ 16-bit

RISC microcontroller cores; 64KB of flash memory,

11KB RAM, and independent hardware stacks; gener-

al-purpose registers; and data pointers for each core.

Application-specific peripherals include hardware SPI

and I

C masters, real-time clock, programmable pulse

generators, dual UARTs (one of which that supports IR

carrier frequency modulation), and math accelerators.

At the heart of the MAXQ3108 are two MAXQ20 16-bit

RISC microcontrollers. The dual-core approach allows

one core (DSPCore) to be entirely dedicated to collec-

tion and processing of AFE samples for the metering

function, while the second core handles any communi-

cation and user-specific administrative functions. The

MAXQ3108 DSPCore operates at 10.027MHz with the

default crystal and almost all instructions execute in a

single clock cycle (100ns), while the UserCore runs at

half that frequency (5.014MHz).

The dual-core strategy promotes flexibility by allowing

the update of metering routines and parameters sepa-

rately in DSPCore code and data memory. Furthermore,

an independent DSPCore solely responsible for accu-

rate metering introduces a measure of safety and relia-

bility since all administrative/communication functions

and interruptions are handled by the UserCore. Both

cores feature standard MAXQ power-saving system

clock-divide modes and independently implement low-

power stop (UserCore) and idle (DSPCore) modes. The

DSPCore implements an idle mode that allows CPU

execution to be halted while awaiting an ADC sample.

The UserCore implements an ultra-low-power stop

mode that automatically disables the DSPCore and

results in a quiescent current consumption of less than

1.5μA. The combination of high performance and core-

specific low-power mode implementation provides

increased power efficiency and capability over compet-

itive microcontrollers.

Microprocessor

The MAXQ20 is a low-power implementation of the new

16-bit MAXQ family of RISC cores. The core supports

the Harvard memory architecture with separate 16-bit

program and data address buses, but also provides

pseudo-Von Neumann support through utility ROM

functions. A fixed 16-bit instruction is standard, but

data can be arranged in 8 or 16 bits. The MAXQ20 core

is implemented as a nonpipelined processor with single

clock-cycle instruction execution. The data path is

implemented around register modules, and each regis-

ter module contributes specific functions to the core.

The accumulator module consists of sixteen 16-bit reg-

isters and is tightly coupled to the arithmetic logic unit

(ALU). Program flow is supported by a dedicated 16-

level-deep hardware stack.

Execution of instructions is triggered by data transfer

between functional register modules, or between a

functional register module and memory. Since data

Pin Description (continued)

PIN NAME FUNCTION

Port 2. Port 2 functions as both a 7-bit I/O port and as a special function interface to the CF pulse

generator outputs, clock output, and the Manchester ENDEC or SPI. The default reset condition of

the pins is weakly pulled up (input), with exception of P2.5 and P2.6, which are always outputs

and default to strong high. To drive output, either the port direction register must be programmed

to enable output, or the alternate function module must be configured to drive the pins. P2.5 and

P2.6 are accessible to the DSPCore only.

PIN PORT ALTERNATE FUNCTION

1 P2.0 MDIN2P/MOSI

28 P2.1 MDIN2N/MISO

27 P2.2 SCLK/CLKO

26 P2.3 MDIN0N/SSEL

25 P2.4 MDIN0P

8 P2.5 CF1

1, 28, 27, 26,

25, 8, 9

P2.0–P2.6

9 P2.6 CF2

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 63 64

MAXQ3108 1

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