MAXQ3108
Low-Power, Dual-Core Microcontroller
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PIN PRIMARY SECONDARY TERTIARY COMMENT
5 P0.3 MDIN1P T2PB
Do not enable outputs or clock gating on timer 2 when Manchester
decoder 1 is enabled. Also, do not enable INT3 when Manchester
decoder 1 is enabled or clock gating is used on Timer 2.
6 P0.4 SDA INT4 Do not enable INT4 when the I
2
C peripheral is in use.
7 P0.5 SCL INT5 Do not enable INT5 when the I
2
C peripheral is in use.
8 P2.5 CF1 — Enabling pulse output 1 disables GPIO-port function on this port.
9 P2.6 CF2 — Enabling pulse output 2 disables GPIO-port function on this port.
10 P1.0 TMS INT8
When JTAG is in use, port pin 1.0 is unavailable. Do not enable INT8
when JTAG is active.
11 P1.1 TCK INT9
When JTAG is in use, port pin 1.1 is unavailable. Do not enable INT9
when JTAG is active.
12 P1.2 TDI INT10
When JTAG is in use, port pin 1.2 is unavailable. Do not enable INT10
when JTAG is active.
13 P1.3 TDO SQW
When JTAG is in use, port pin 1.3 and the SQW function are unavailable.
Do not enable INT11 when either JTAG or the SQW function is active.
14 P1.4 TBB — When using TBB as an input, P1.4 must be configured as an input.
18 P1.5 TBA —
When using TBA as either an input or output, P1.5 must be configured as
an input.
22 P0.7 RXD1 INT7
Receive data function is only operational when the associated REN bit is
set is the SCON1 register. Do not enable an interrupt on this pin if it is
used for the serial receive function.
23 P0.6 TXD1 INT6
Transmit data is only presented to the pin when a character is actually
being transmitted. To use this pin as full-time transmit data, set the GPIO
port pin to output and load a 1 in the output register. Do not enable an
interrupt on this pin if it is used for the serial transmit function.
24 P1.6 RST —
This is an active-low reset pin. Driving a low level on P1.6 causes the
MAXQ3108 to reset. The reset function on this pin can be disabled by
setting RSTD to 1.
25 P2.4 MDIN0P — When Manchester decoder 0 is enabled, set P2.4 as an input.
26 P2.3 MDIN0N SSEL When using Manchester decoder 0, disable SPI and set P2.3 as an input.`
27 P2.2 SCLK CLKO
When CLKO (system clock for the CPU core) is enabled (that is, the
ECLKO bit is set), the SPI peripheral cannot be used.
28 P2.1 MDIN2N MISO
When the Manchester decoder 2 is used, the SPI peripheral cannot be
used. The P2.1 port pin should be set to an input when using Manchester
decoder 2.
Table 5. Multipurpose Pin Description (continued)
Clock
All functional units in the MAXQ3108 are synchronized
to the system clock. The system clock can be generat-
ed from an internal oscillator with a 32,768Hz external
crystal/resonator or an internal FLL oscillator. The basic
unit of time in the MAXQ3108 is the system clock peri-
od. The UserCore receives a system clock that is one-
half the internal clock frequency. The Manchester
decoders, cubic sinc filters, and the DSPCore all
receive the undivided system clock.
The internal clock circuitry generates the system clock
from one of the two clock sources:
• Internal oscillator with a 32,768Hz external crystal or
resonator
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