
MAXQ3108
Low-Power, Dual-Core Microcontroller
16 ______________________________________________________________________________________
BIT
REGISTER
MOD:
REG
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PO2 1:7 Port 2 Output Register
MC1R 1:8 Multiplier Read Register 1 (MSB, bits 31-16)
MC0R 1:9 Multiplier Read Register 0 (LSB, bits 15-0)
CF1D 1:12 CF1 Delay Register
CF2D 1:13 CF2 Delay Register
Table 3. DSPCore Peripheral Registers (continued)
BIT
REGISTER
MOD:
REG
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AD0 0:0 0xFFFF
AD1 0:1 0xFFFF
AD2 0:2 0xFFFF
AD3 0:3 0xFFFF
AD4 0:4 0xFFFF
AD5 0:5 0xFFFF
SRSP0 0:6 0 0 0x0
SRSP1 0:7 0x0000
AD0LSB 0:8 0xFF
AD1LSB 0:9 0xFF
AD2LSB 0:10 0xFF
AD3LSB 0:11 0xFF
AD4LSB 0:12 0xFF
AD5LSB 0:13 0xFF
MREQ0 0:14 0 0 0x0
MREQ1 0:15 0x0000
MREQ2 0:16 0x0000
ADCN 0:17 0 0 0 0 0 0 0 0 0x0 0 0 0 0 0 0
ADCC 0:18 0x0000
MSTC 0:19 0x3 0 0 0
MCNT 1:0 0 0 0 0 0 0 0 0
MA 1:1 0x0000
MB 1:2 0x0000
MC2 1:3 0x0000
MC1 1:4 0x0000
MC0 1:5 0x0000
PO2 1:7 0x0000
MC1R 1:8 0x0000
MC0R 1:9 0x0000
CF1D 1:12 0x0000
CF2D 1:13 0x0000
Table 4. DSPCore Peripheral Register Default Values
Comentários a estes Manuais