MAXQ3108
Low-Power, Dual-Core Microcontroller
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Special Function Register Bit Descriptions (continued)
PI0 (02h, 01h) Port 0 Input Register
Initialization: The reset value for this register is dependent on the logical states of the pins.
Read/Write Access: Unrestricted read-only.
PI0.[7:0]:
Port 0 Input Register Bits 7:0. The PI0 register always reflects the logic state of its pins when read.
Note that each port pin has a weak pullup circuit when functioning as an input and the p-channel
pullup transistor is controlled by its respective PO bits. If the PO bit is set to 1, the weak pullup is
on, if the PO bit is cleared to 0, the weak pullup is off and forces the port pin into three-state.
PI1 (03h, 01h) Port 1 Input Register
Initialization: The reset value for this register is 0sssssssb, where “s” depends on the logical state of the pin.
Read/Write Access: Unrestricted read.
PI1.[6:0]:
Port 1 Input Register Bits 6:0. The PI1 register always reflects the logic state of its pins when read.
Note that each port pin has a weak pullup circuit when functioning as an input and the p-channel
pullup transistor is controlled by its respective PO bits. If the PO bit is set to 1, the weak pullup is
on, if the PO bit is cleared to 0, the weak pullup is off and forces the port pin into three-state.
PI1.7: Reserved Reserved. Read returns 0.
EIF0 (04h, 01h) External Interrupt Flag 0 Register
Initialization: EIF0 is cleared to 00h on all forms of reset.
Read/Write Access: Unrestricted read/write.
EIF0.[7:0]: IE[7:0]
Interrupt Edge Detect Bits 7:0. These bits are set when a negative edge (ITx = 1) or a positive
edge (ITx = 0) is detected on the interrupt x pin. Setting any of the bits to 1 generates an interrupt to
the CPU if the corresponding interrupt is enabled. This bit remains set until cleared by software or a
reset. It must be cleared by software before exiting the interrupt source routine or another interrupt
is generated as long as the bit remains set.
EIE0 (05h, 01h) External Interrupt Enable 0 Register
Initialization: EIE0 is cleared to 00h on all forms of reset.
Read/Write Access: Unrestricted read/write.
EIE0.[7:0]: EX[7:0]
Enable External Interrupt Bits 7:0. Setting any of these bits to 1 enables the corresponding
external interrupt. Clearing any of the bits to 0 disables the corresponding interrupt function.
EIF1 (06h, 01h) External Interrupt Flag 1 Register
Initialization: EIF1 is cleared to 00h on all forms of reset.
Read/Write Access: Unrestricted read/write.
EIF1.[3:0]: IE[11:8]
Interrupt Edge Detect Bits 11:8. These bits are set when a negative edge (ITx = 1) or a positive
edge (ITx = 0) is detected on the interrupt x pin. Setting any of the bits to 1 generates an interrupt to
the CPU if the corresponding interrupt is enabled. This bit remains set until cleared by software or a
reset. It must be cleared by software before exiting the interrupt source routine or another interrupt
is generated as long as the bit remains set.
EIF1.[7:4]: Reserved Reserved. Reads return 0.
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