Rainbow-electronics ATmega64C1 Manual do Utilizador Página 158
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7647A–AVR–02/08
ATmega32/64/M1/C1
the required clock pulses on the SCK line to interchange data. Data is always shifted from Mas-
ter to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In
– Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling
high the Slave Select, SS
, line.
When configured as a Master, the SPI interface has no automatic control of the SS
line. This
must be handled by user software before communication can start. When this is done, writing a
byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight
bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of
transmission flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an
interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or
signal the end of packet by pulling high the Slave Select, SS
line. The last incoming byte will be
kept in the Buffer Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long
as the SS
pin is driven high. In this state, software may update the contents of the SPI Data
Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin
until the SS
pin is driven low. As one byte has been completely shifted, the end of transmission
flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is
requested. The Slave may continue to place new data to be sent into SPDR before reading the
incoming data. The last incoming byte will be kept in the Buffer Register for later use.
Figure 15-2. SPI Master-slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive direc-
tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before
the entire shift cycle is completed. When receiving data, however, a received character must be
read from the SPI Data Register before the next character has been completely shifted in. Oth-
erwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure
correct sampling of the clock signal, the frequency of the SPI clock should never exceed f
clkio
/4.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS
pins is overridden
according to Table 15-1. For more details on automatic port overrides, refer to “Alternate Port
Functions” on page 65.
Table 15-1. SPI Pin Overrides
(1)
Pin Direction, Master SPI Direction, Slave SPI
MOSI User Defined Input
SHIFT
ENABLE
- Features 1
- ATmega32/64/M1/C1 10
- 7.4 Watchdog Timer 50
- 9. I/O-Ports 60
- DATA BUS 61
- INSTRUCTIONS 63
- SYNC LATCH 63
- SYSTEM CLK 63
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