Rainbow-electronics AT91CAP9S250A Manual do Utilizador

Features• Incorporates the ARM926EJ-S™ ARM® Thumb® Processor– DSP Instruction Extensions, ARM Jazelle® Technology for Java® Acceleration– 16 Kbyte Dat

106264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A4. Package and PinoutThe AT91CAP9S500A/AT91CAP9S250A is available in a 400-ball RoHS-compliant BGA pac

1006264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-timeValue Regis

iv6264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A19.5 Functional Description ...1

v6264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.4 Functional Description ...21

vi6264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.4 USB Clock Controller ...3

vii6264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.7 Serial Peripheral Interface (SPI) User Interface ...47034 Two-wi

viii6264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.6 Functional Description ...

ix6264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.10 MultiMedia Card Interface (MCI) User Interface ...77442 10/100 Ethe

x6264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.3 Power Consumption ...960

xi6264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,

1016264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A16.4 Real-time Timer (RTT) User InterfaceTable 16-1. Real-time Timer Register MappingOffset Register

1026264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A16.4.1 Real-time Timer Mode RegisterRegister Name: RTT_MRAccess Type: Read/Write• RTPRES: Real-time

1036264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A16.4.2 Real-time Timer Alarm RegisterRegister Name: RTT_ARAccess Type: Read/Write• ALMV: Alarm Valu

1046264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A16.4.4 Real-time Timer Status RegisterRegister Name: RTT_SRAccess Type: Read-only• ALMS: Real-time

1056264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A17. Periodic Interval Timer (PIT)17.1 OverviewThe Periodic Interval Timer (PIT) provides the operatin

1066264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A17.3 Functional DescriptionThe Periodic Interval Timer aims at providing periodic interrupts for use

1076264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 17-2. Enabling/Disabling PIT with PITEN MCK Prescaler PIVPIV - 10PITEN10015CPIV1restarts MCK P

1086264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A17.4 Periodic Interval Timer (PIT) User InterfaceTable 17-1. Periodic Interval Timer (PIT) Register M

1096264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A17.4.1 Periodic Interval Timer Mode RegisterRegister Name: PIT_MRAccess Type: Read/Write• PIV: Perio

116264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A4.2 400-ball BGA Package Pinout Table 4-1. AT91CAP9S500A/AT91CAP9S250A Pinout for 400-ball BGA Package

1106264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A17.4.2 Periodic Interval Timer Status RegisterRegister Name: PIT_SRAccess Type: Read-only• PITS: Pe

1116264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A17.4.4 Periodic Interval Timer Image RegisterRegister Name: PIT_PIIRAccess Type: Read-only • CPIV:

1126264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

1136264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A18. Watchdog Timer (WDT)18.1 DescriptionThe Watchdog Timer can be used to prevent system lock-up if t

1146264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A18.3 Functional DescriptionThe Watchdog Timer can be used to prevent system lock-up if the software b

1156264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 18-2. Watchdog Behavior 0WDVWDDWDT_CR = WDRSTTWatchdog FaultNormal behavior Watchdog Error Wa

1166264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A18.4 Watchdog Timer (WDT) User Interface Table 18-1. Watchdog Timer RegistersOffset Register Name Ac

1176264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A18.4.1 Watchdog Timer Control RegisterRegister Name: WDT_CRAccess Type: Write-only • WDRSTT: Watch

1186264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A18.4.2 Watchdog Timer Mode RegisterRegister Name: WDT_MRAccess Type: Read/Write Once• WDV: Watch

1196264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A18.4.3 Watchdog Timer Status RegisterRegister Name: WDT_SRAccess Type: Read-only• WDUNF: Watchdog U

126264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AB18 GNDIO G18 GNDCORE M18 MPIOB27 U18 MPIOA28B19 VDDUTMII G19 TST M19 MPIOB25 U19 MPIOB6B20 GNDUTMII G

1206264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

1216264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A19. Shutdown Controller (SHDWC)19.1 DescriptionThe Shutdown Controller controls the power supplies VD

1226264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AA typical application connects the pin SHDN to the shutdown input of the DC/DC Converter pro-viding t

1236264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A19.6 Shutdown Controller (SHDWC) User Interface19.6.1 Register Mapping19.6.2 Shutdown Control Registe

1246264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A19.6.3 Shutdown Mode RegisterRegister Name: SHDW_MRAccess Type: Read/Write • WKMODE0: Wake-up Mode

1256264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A19.6.4 Shutdown Status RegisterRegister Name: SHDW_SRAccess Type: Read-only • WAKEUP0: Wake-up 0 St

1266264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

1276264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

1286264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

1296264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A20. Bus Matrix20.1 DescriptionThe Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol

136264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A5. Power Considerations5.1 Power SuppliesThe AT91CAP9S500A/AT91CAP9S250A has several types of power su

1306264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe 2-bit DEFMSTR_TYPE field selects the default master type (no default, last access mas-ter, fixed

1316264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary

1326264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A20.4.3 Fixed Priority ArbitrationThis algorithm allows the Bus Matrix arbiters to dispatch the reques

1336264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A20.5 Bus Matrix User Interface Table 20-1. Register Mapping Offset Register Name Access Reset Value0x

1346264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A0x00AC Priority Register B for Slave 5 MATRIX_PRBS5 Read/Write 0x000000000x00B0 Priority Register A f

1356264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A20.5.1 Bus Matrix Master Configuration RegistersRegister Name: MATRIX_MCFG0...MATRIX_MCFG11Access Typ

1366264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A20.5.2 Bus Matrix Slave Configuration RegistersRegister Name: MATRIX_SCFG0...MATRIX_SCFG9Access Type:

1376264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A20.5.3 Bus Matrix Priority Registers A For SlavesRegister Name: MATRIX_PRAS0...MATRIX_PRAS9Access Typ

1386264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A20.5.5 Bus Matrix Master Remap Control RegisterRegister Name: MATRIX_MRCRAccess Type: Read/WriteReset

1396264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A20.6 Chip Configuration User Interface20.6.1 MPBlock Slave 0 Special Function RegisterRegister Name:

146264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• VDDIOMPA pins: Power the MP Block I/O A lines; voltage ranges from 1.65V to 3.6V, 1.8V, 2.5V, 3V or

1406264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• MPBS0_SFR: MPBlock Slave 1 Special Function RegisterThe value of the register is directy connected

1416264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A20.6.4 MPBlock Slave 2 Special Function RegisterRegister Name: MPBS2_SFRAccess Type: Read/WriteReset:

1426264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A20.6.6 APB Bridge Special Function RegisterRegister Name: APB_SFRAccess Type: Read/WriteReset: 0x0000

1436264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21. External Bus Interface (EBI)21.1 DescriptionThe External Bus Interface (EBI) is designed to ensur

1446264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 21-1. Organization of the External Bus InterfaceExternal Bus InterfaceD[15:0]A[15:2], A[22:18]

1456264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21.2 I/O Lines DescriptionTable 21-1. EBI I/O Lines DescriptionName Function Type Active LevelEBID0 -

1466264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ABCCK Burst CellularRAM Clock OutputBCCRE Burst CellularRAM Clock Enable Output HighBCCS Burst Cellula

1476264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21.3 Application Example21.3.1 Hardware InterfaceTable 21-2 on page 147 details the connections to be

1486264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ATable 21-3. EBI Pins and External Devices ConnectionsSignalsPins of the Interfaced DeviceSDRAM Mobile

1496264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ANote: 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional bu

156264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A6. I/O Line Considerations6.1 JTAG Port PinsTMS, TDI and TCK are Schmitt trigger inputs and have no pu

1506264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21.5.1 Bus MultiplexingThe EBI offers a complete set of control signals that share the 32-bit data li

1516264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21.5.8.1 I/O Mode, Common Memory Mode, Attribute Memory Mode and True IDE ModeWithin the NCS4 and/or

1526264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. Fordetails on these w

1536264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 21-3. CompactFlash Read/Write Control Signals21.5.8.4 Multiplexing of CompactFlash Signals on

1546264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21.5.8.5 Application ExampleFigure 21-4 on page 154 illustrates an example of a CompactFlash applicat

1556264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21.5.9 NAND Flash SupportExternal Bus Interface integrates circuitry that interfaces to NAND Flash de

1566264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 21-6. NAND Flash Application ExampleD[7:0]ALENANDWENANDOENOENWEA[22:21]CLEAD[7:0]PIOR/BEBICENA

1576264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21.6 Implementation Examples21.6.1 16-bit SDRAM21.6.1.1 Hardware Configuration21.6.1.2 Software Confi

1586264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21.6.2 32-bit SDRAM21.6.2.1 Hardware Configuration21.6.2.2 Software ConfigurationThe following config

1596264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21.6.3 16-bit Mobile DDR21.6.3.1 Hardware Configuration21.6.3.2 Software ConfigurationThe following c

166264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A7. Processor and Architecture7.1 ARM926EJ-S Processor• RISC Processor based on ARM v5TEJ Architecture

1606264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21.6.4 16-bit BCRAM21.6.4.1 Hardware Configuration21.6.4.2 Software ConfigurationThe following config

1616264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21.6.5 8-bit NAND Flash21.6.5.1 Hardware Configuration21.6.5.2 Software ConfigurationThe following co

1626264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21.6.6 16-bit NAND Flash21.6.6.1 Hardware Configuration21.6.6.2 Software ConfigurationThe software co

1636264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21.6.7 NOR Flash on NCS021.6.7.1 Hardware Configuration21.6.7.2 Software ConfigurationThe default con

1646264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21.6.8 Compact Flash21.6.8.1 Hardware ConfigurationD15D14D13D12D10D11D9D8D7D6D5D4D2D1D0D3A10A9A8A7A3A

1656264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21.6.8.2 Software ConfigurationThe following configuration has to be performed:• Assign the EBI CS4 a

1666264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21.6.9 Compact Flash True IDE21.6.9.1 Hardware ConfigurationD15D14D13D12D10D11D9D8D7D6D5D4D2D1D0D3A10

1676264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A21.6.9.2 Software ConfigurationThe following configuration has to be performed:• Assign the EBI CS4 a

1686264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

1696264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22. Static Memory Controller (SMC)22.1 DescriptionThe Static Memory Controller (SMC) generates the si

176264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A– Round-Robin Arbitration, either with no default master, last accessed default master or fixed defaul

1706264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.4 Application Example22.4.1 Hardware InterfaceFigure 22-1. SMC Connections to Static Memory Device

1716264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.6 External Memory MappingThe SMC provides up to 26 address lines, A[25:0]. This allows each chip s

1726264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 22-3. Memory Connection for an 8-bit Data Bus Figure 22-4. Memory Connection for a 16-bit Da

1736264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.7.2.1 Byte Write Access Byte write access supports one byte write signal per byte of the data bus

1746264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 22-6. Connection of 2 x 8-bit Devices on a 16-bit Bus: Byte Write Option22.7.2.3 Signal Multi

1756264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 22-7. Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option) 22.8 Standard

1766264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.8.1 Read WaveformsThe read cycle is shown on Figure 22-8.The read cycle starts with the address se

1776264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.8.1.2 NCS WaveformSimilarly, the NCS signal can be divided into a setup time, pulse length and hol

1786264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 22-9. No Setup, No Hold On NRD and NCS Read Signals22.8.1.5 Null PulseProgramming null pulse i

1796264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 22-10. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD22.8.2.2 Read is Con

186264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe LCD Controller, the DMA Controller, the USB Host and the USB OTG have a user interfacemapped as a

1806264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.8.3 Write WaveformsThe write protocol is similar to the read protocol. It is depicted in Figure 22

1816264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.8.3.3 Write CycleThe write_cycle time is defined as the total duration of the write cycle, that is

1826264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.8.4 Write ModeThe WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select i

1836264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 22-15. WRITE_MODE = 0. The write operation is controlled by NCS22.8.5 Coding Timing Parameters

1846264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.8.6 Reset Values of Timing ParametersTable 22-5 gives the default value of timing parameters at re

1856264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 22-16. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2 22.9.2

1866264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 22-17. Early Read Wait State: Write with No Hold Followed by Read with No SetupFigure 22-18. E

1876264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 22-19. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Se

1886264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.9.4 Read to Write Wait StateDue to an internal mechanism, a wait cycle is always inserted between

1896264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.10 Data Float Wait StatesSome memory devices are slow to release the external bus. For such device

196264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A Note: 1. DDR Port 2 or Port 3 is selectable for each master through the Matrix Remap Control Register

1906264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 22-20. TDF Period in NRD Controlled Read Access (TDF = 2)Figure 22-21. TDF Period in NCS Contr

1916264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.10.2 TDF Optimization Enabled (TDF_MODE = 1)When the TDF_MODE of the SMC_MODE register is set to 1

1926264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 22-23. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on di

1936264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 22-25. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select22

1946264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.11.2 Frozen ModeWhen the external device asserts the NWAIT signal (active low), and after internal

1956264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 22-27. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)EXNW_MODE = 10 (Frozen)

1966264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.11.3 Ready ModeIn Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begi

1976264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 22-29. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11)EXNW_MODE = 11(Ready mode)RE

1986264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.11.4 NWAIT Latency and Read/write TimingsThere may be a latency between the assertion of the read/

1996264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.12 Slow Clock ModeThe SMC is able to automatically apply a set of “slow clock mode” read/write wav

26264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A– Four 32-bit Battery Backup Registers for a Total of 16 Bytes– Clock Generator and Power Management Co

206264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A7.6 Peripheral DMA Controller• Acting as one Matrix Master • Allows data transfers from/to peripheral

2006264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.12.2 Switching from (to) Slow Clock Mode to (from) Normal ModeWhen switching from slow clock mode

2016264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 22-33. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode

2026264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.13 Asynchronous Page ModeThe SMC supports asynchronous burst reads in page mode, providing that th

2036264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ANCS_RD_PULSE field of the SMC_PULSE register. The pulse length of subsequent accesseswithin the page

2046264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 22-35. Access to Non-sequential Data within the Same Page A[25:3]A[2], A1, A0NCSMCKNRDPage ad

2056264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.14 Static Memory Controller (SMC) User InterfaceThe SMC is programmed using the registers listed i

2066264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.14.1 SMC Setup RegisterRegister Name: SMC_SETUP[0 ..5]Access Type: Read/Write• NWE_SETUP: NWE Setu

2076264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.14.2 SMC Pulse RegisterRegister Name: SMC_PULSE[0..5]Access Type: Read/Write• NWE_PULSE: NWE Pulse

2086264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.14.3 SMC Cycle RegisterRegister Name: SMC_CYCLE[0..5]Access Type: Read/Write • NWE_CYCLE: Total Wr

2096264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A22.14.4 SMC MODE RegisterRegister Name: SMC_MODE[0..5]Access Type: Read/Write• READ_MODE:1: The read

216264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• Embeds 4 unidirectional channels with programmable priority• Address Generation– Source / destinatio

2106264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• BAT: Byte Access TypeThis field is used only if DBW defines a 16- or 32-bit data bus.• 1: Byte wri

2116264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23. DDR/SDR SDRAM Controller (DDRSDRC)23.1 DescriptionThe DDR/SDR SDRAM Controller (DDRSDRC) is a mul

2126264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.2 DDRSDRC Module DiagramFigure 23-1. DDRSDRC Module Diagram DDRSDRC is partitioned in two blocks

2136264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.3 Product DependenciesThe addresses given are for example purposes only. The real address depends

2146264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Atimer count register must to be set with (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81 /100 MHz) = 78

2156264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A11. A Mode Register set (MRS) cycle is issued to program the parameters of the DDR-SDRAM devices, in

2166264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A8. A Mode Register set (MRS) cycle is issued to program the parameters of the DDR-SDRAM devices, in p

2176264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFor a definition of timing parameters, refer to Section 23.6.4 ”DDRSDRC Timing 0 ParameterRegister” o

2186264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 23-3. Single Write Access, Row Closed, SDR-SDRAM DeviceFigure 23-4. Burst Write Access, Row Cl

2196264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 23-5. Burst Write Access, Row Closed, SDR-SDRAM DevicesRow a Col aNOP PRCHG NOP ACT NOP WRITEN

226264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A8. MemoriesFigure 8-1. AT91CAP9S500A/AT91CAP9S250A Memory MappingDMAMPB SLAVE1SRAMMPB SLAVE0ROMMPB SLA

2206264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AA write command can be followed by a read command. To avoid breaking the current writeburst, Twtr/twr

2216264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.4.2 SDRAM Controller Read CycleThe DDRSDRC allows burst access or single access in normal mode (mo

2226264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Aaccount this feature of the SDRAM device. In the case of DDR-SDRAM devices, transfers startat address

2236264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 23-10. Burst Read Access, Latency =2, DDR-SDRAM DevicesFigure 23-11. Burst Read Access, Latenc

2246264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.4.3 Refresh (Auto-refresh Command)An auto-refresh command is used to refresh the DDRSDRC. Refresh

2256264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 23-12. Self Refresh Mode Entry, Timeout =0Figure 23-13. Self Refresh Mode Entry, Timeout =1 or

2266264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.4.4.2 Power-down ModeThis mode is activated by setting the low-power command bits [LPCB] to ‘10’.P

2276264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.4.4.3 Deep Power-down ModeThe deep power-down mode is a new feature of the Mobile SDRAM. When this

2286264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.4.4.4 Multi-port Functionality The SDRAM protocol imposes a check of timings prior to performing a

2296264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A1. Idle cycles: When no master is connected to the SDRAM device.2. Single cycles: When a slave is cur

236264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AA first level of address decoding is performed by the Bus Matrix, i.e., the implementation of theAdvan

2306264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.5 Software Interface / SDRAM Organization, Address MappingThe SDRAM address space is organized int

2316264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ANote: 1. SDR-SDRAM devices with eight columns in 16-bit mode are not supported. 23.5.2 SDR-SDRAM Addr

2326264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.6 DDR-SDRAMC User InterfaceThe User Interface is connected to the APB bus. The DDRSDRC is programm

2336264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.6.1 DDRSDRC Mode RegisterRegister Name: DDRSDRC_MRAccess Type: Read/WriteReset Value: See Table 23

2346264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.6.2 DDRSDRC Refresh Timer RegisterRegister Name: DDRSDRC_TRAccess Type: Read/WriteReset Value: See

2356264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.6.3 DDRSDRC Configuration RegisterRegister Name: DDRSDRC_CRAccess Type: Read/WriteReset Value: See

2366264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• DLL: Reset DLLReset value is 0.This field defines the value of Reset DLL. 0: Disable DLL reset 1: E

2376264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.6.4 DDRSDRC Timing 0 Parameter RegisterRegister Name: DDRSDRC_T0PRAccess Type: Read/WriteReset Val

2386264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• TWTR: Internal write to read delayReset value is 0.This field defines the internal write to read co

2396264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.6.5 DDRSDRC Timing 1 Parameter RegisterRegister Name: DDRSDRC_T1PRAccess Type: Read/WriteReset Val

246264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A8.1.1.1 Internal 32 Kbyte Fast SRAMThe AT91CAP9S500A/AT91CAP9S250A integrates a 32 Kbyte SRAM, mapped

2406264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.6.6 DDRSDRC Low-power RegisterRegister Name: DDRSDRC_LPRAccess Type: Read/WriteReset Value: See Ta

2416264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThis field is unique to Mobile SDRAM. It is used to program the refresh interval during self refresh

2426264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.6.7 DDRSDRC Memory Device RegisterRegister Name: DDRSDRC_MDAccess Type: Read/WriteReset Value: See

2436264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A23.6.8 DDRSDRC DLL InformationRegister Name: DDRSDRC_DLLAccess Type: ReadReset Value: See Table 23-8T

2446264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A1: The DLL has not succeeded in computing the Slave delay correction.•MDVAL: DLL Master Delay ValueVa

2456264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A24. Burst Cellular RAM Controller (BCRAMC)24.1 DescriptionThe Burst Cellular RAM Controller (BCRAMC)

2466264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A24.2 BCRAMC Block DiagramFigure 24-1. BCRAMC Block Diagram Memory Controller Signal ManagementAddrAPB

2476264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A24.3 Product Dependencies24.3.1 Cellular Ram InitializationThe Cellular Ram devices are initialized

2486264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A24.4 Functional Description24.4.1 BCRAMC OverviewThe BCRAMC is a synchronous cellular RAM controller,

2496264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Aparameters, additional clock cycles are inserted to check programmed latency. A single accessowait si

256264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A8.2.1 External Bus InterfaceThe AT91CAP9S500A/AT91CAP9S250A features one External Bus Interface to off

2506264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 24-4. Single Write Access with Refresh Collision Figure 24-5. Burst Write Access with No Refre

2516264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 24-6. Four Beat Wrapping Burst With Address Starting at 0x0C Figure 24-7. Write Command Follow

2526264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Alatency. The BCRAMC supports latency value which is a function of the Cellular Ram version.The owait

2536264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 24-8. Single Read Access with Refresh CollisionFigure 24-9. Single Read Access with No Refresh

2546264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 24-10. Burst Read Access with No Refresh CollisionFigure 24-11. Four Beat Wrapping Burst with

2556264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A24.4.4 Power Management24.4.4.1 Standby ModeThis mode is activated by programming low power command b

2566264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A24.4.4.3 Temperature Compensated Refresh (TCR) or Temperature Compensated Self-refresh (TCSR)This fea

2576264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A24.5 BCRAMC User InterfaceThe User interface is connected to the APB bus. The BCRAMC is programmed us

2586264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A24.5.1 BCRAMC Configuration RegisterRegister Name: BCRAMC_CRAccess Type: Read/Write• CRAM_EN: BCRAMC

2596264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThis field manages the row boundaries. Some Cellular Ram providers do not provide the number of word

266264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A– SDRAM with 16- or 32-bit Data Path– Mobile DDR with four Internal Banks– Mobile DDR with 16-bit Data

2606264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A24.5.2 BCRAMC Timing RegisterRegister Name: BCRAMC_TRAccess Type: Read/Write• TCW: Chip Enable to End

2616264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

2626264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A24.5.3 BCRAMC Low Power RegisterRegister Name: BCRAMC_LPRAccess Type: Read/Write• PAR: Partial Array

2636264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A11: reserved24.5.4 BCRAMC Memory Device RegisterRegister Name: BCRAMC_MDAccess Type: Read/Write• MD

2646264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A24.5.6 BCRAMC Name1 RegisterRegister Name: BCRAMC_IPNAME1Access Type: Read-only •IPNAMEReserved. Val

2656264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A24.5.8 BCRAMC Features RegisterRegister Name: BCRAMC_FEATURESAccess Type: Read-onlyReserved.31 30 29

2666264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

2676264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A25. Error Corrected Code (ECC) Controller25.1 Description NAND Flash/SmartMedia devices contain by de

2686264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe only configuration required for ECC is the NAND Flash or the SmartMedia page size(528/1056/2112/4

2696264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 25-2. Parity Generation for 512/1024/2048/4096 8-bit Words1 To calculate P8’ to PX’ and P8 to

276264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A8.2.5 Error Corrected Code Controller• Tracking the accesses to a NAND Flash device by trigging on the

2706264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 25-3. Parity Generation for 512/1024/2048/4096 16-bit Words 1st word2nd word3rd word4th word(P

2716264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ATo calculate P8’ to PX’ and P8 to PX, apply the algorithm that follows.Page size = 2n for i =0 to n

2726264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A25.4 Error Corrected Code (ECC) Controller User Interface Table 25-1. ECC Register MappingOffset Regi

2736264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A25.4.1 ECC Control RegisterName: ECC_CRAccess Type: Write-only• RST: RESET ParityProvides reset to cu

2746264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A25.4.3 ECC Status RegisterRegister Name: ECC_SRAccess Type: Read-only• RECERR: Recoverable Error0 = N

2756264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A25.4.4 ECC Parity RegisterRegister Name: ECC_PRAccess Type: Read-onlyOnce the entire main area of a p

2766264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

2776264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26. DMA Controller (DMAC)26.1 DescriptionThe DMA Controller (DMAC) is an AHB-central DMA controller c

2786264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.2 Block DiagramFigure 26-1. DMA Controller (DMAC) Block DiagramDMA DestinationDMA Channel 0DMA Des

2796264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 26-2. DMA Controller (DMAC) Block DiagramDMA DestinationDMA Channel 0DMA DestinationControl St

286264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A9.1 System Controller Block DiagramFigure 9-1. AT91CAP9S500A/AT91CAP9S250A System Controller Block Dia

2806264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.3 Functional Description26.3.1 Basic DefinitionsSource peripheral: Device on an AMBA layer from wh

2816264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 26-3. DMAC Transfer Hierarchy for Non-Memory PeripheralFigure 26-4. DMAC Transfer Hierarchy fo

2826264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Aan interrupt to signal the completion of the DMAC transfer. You can then re-program the channelfor a

2836264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ABus locking: Software can program a channel to maintain control of the AMBA bus by assertinghmastlock

2846264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.3.3.3 Single TransactionsWriting a 1 to the DMAC_SREQ[2x] register starts a source single transact

2856264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.3.4 DMAC Transfer TypesA DMAC transfer may consist of single or multi-buffers transfers. On succes

2866264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 26-6. Multi Buffer Transfer Using Linked List System MemorySADDRx= DSCRx(0) + 0x0DADDRx= DSCRx

2876264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.3.4.3 Programming DMAC for Multiple Buffer Transfers Notes: 1. USR means that the register field i

2886264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Abuffers is a function of DMAC_CTRLAx.SRC_DSCR, DMAC_CFGx.SRC_REP,DMAC_CTRLAx.DST_DSCR and DMAC_CFGx.D

2896264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.3.5 Programming a ChannelFour registers, the DMAC_DSCRx, the DMAC_CTRLAx, the DMAC_CTRLBx andDMAC_

296264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A9.2 Reset Controller• Based on two Power-on-Reset cells– One on VDDBU and one on VDDCORE• Status of th

2906264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A– ii. If the hardware handshaking interface is activated for the source or destination peripheral, as

2916264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ALLI.DMAC_CTRLBx register of the last Linked List Item must be set as described in Row 1 of Table 26-1

2926264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 26-7. Multi-buffer with Linked List Address for Source and DestinationIf the user needs to exe

2936264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 26-8. Multi-buffer with Linked Address for Source and Destination Buffers are ContiguousThe DM

2946264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 26-9. DMAC Transfer Flow for Source and Destination Linked List Address26.3.5.4 Multi-buffer T

2956264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Aa. Write the starting source address in the DMAC_SADDRx register for channel x.b. Write the starting

2966264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AChannel Enable in the Channel Status Register (DMAC_CHSR.ENABLE[n]) until it is disabled, to detect w

2976264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 26-11. DMAC Transfer Flow for Source and Destination Address Auto-reloaded26.3.5.5 Multi-buffe

2986264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A3. Write the starting source address in the DMAC_SADDRx register for channel x.Note: The values in th

2996264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Atransfer. Only DMAC_CTRLAx register is written out, because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRL

36264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• One AC97 Controller (AC97C)– 6-channel Single AC97 Analog Front End Interface, Slot Assigner• Three U

306264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A9.5 Power Management Controller•Provides:– the Processor Clock PCK– the Master Clock MCK, in particula

3006264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 26-13. DMAC Transfer Flow for Replay Mode at Source and Linked List Destination Address26.3.5.

3016264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A– ii. Set up the transfer characteristics, such as:– Transfer width for the source in the SRC_WIDTH f

3026264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Aautomatic transfer mode bit should remain enabled to keep the DMAC in Row 11 as shown in Table 26-1 o

3036264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 26-15. DMAC Transfer Replay Mode is Enabled for the Source and Contiguous Destination Address2

3046264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A– v. Incrementing/decrementing or fixed address for source in SRC_INCR field.– vi. Incrementing/decre

3056264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Athe linked list item fetched prior to the start of the buffer transfer. Only DMAC_CTRLAx register is

3066264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 26-17. DMAC Transfer Flow for Linked List Source Address and Contiguous Destination Address26.

3076264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A1. If software wishes to disable a channel n prior to the DMAC transfer completion, then it can set t

3086264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• When destination peripheral is defined as the flow controller, if the destination width is smaller

3096264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5 DMA Controller (DMAC) User InterfaceTable 26-2. DMAC Register MappingOffset Register Name Access

316264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A9.7 Watchdog Timer• 16-bit key-protected only-once-Programmable Counter• Windowed, prevents the proces

3106264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A0x07CDMAC Channel 1 Source Picture in Picture Configuration RegisterDMAC_SPIP1 Read/Write 0x00x080DMA

3116264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A0x0F8DMAC Channel 4 Destination Picture in Picture Configuration RegisterDMAC_DPIP4 Read/Write 0x00x0

3126264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A0x174 Reserved – – –0x178 Reserved – – –0x03C - 0x060 Reserved – – –0x064 - 0x088 Reserved – – –0x08C

3136264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.1 DMAC Global Configuration RegisterName: DMAC_GCFGAccess: Read/WriteReset Value: 0x00000010• IF

3146264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.2 DMAC Enable RegisterName: DMAC_ENAccess: Read/WriteReset Value: 0x00000000• ENABLE0: DMA Contr

3156264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.4 DMAC Software Chunk Transfer Request RegisterName: DMAC_CREQAccess: Read/WriteReset Value: 0x0

3166264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable RegisterName: DMAC_EB

3176264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable RegisterName: DMAC_E

3186264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask RegisterName: DMAC_EBCI

3196264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status RegisterName: DMAC_EBCISRAccess

326264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A•Two-pin UART– Implemented features are 100% compatible with the standard Atmel USART– Independent rec

3206264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.10 DMAC Channel Handler Enable RegisterName: DMAC_CHERAccess: Write-onlyReset Value: 0x00000000•

3216264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.11 DMAC Channel Handler Disable RegisterName: DMAC_CHDRAccess: Write-onlyReset Value: 0x00000000

3226264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.12 DMAC Channel Handler Status RegisterName: DMAC_CHSRAccess: Read-onlyReset Value: 0x00FF0000•

3236264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.13 DMAC Channel x [x = 0..3] Source Address RegisterName: DMAC_SADDRx [x = 0..3]Access: Read/Wri

3246264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.14 DMAC Channel x [x = 0..3] Destination Address RegisterName: DMAC_DADDRx [x = 0..3]Access: Rea

3256264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.15 DMAC Channel x [x = 0..3] Descriptor Address RegisterName: DMAC_DSCRx [x = 0..3]Access: Read/

3266264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.16 DMAC Channel x [x = 0..3] Control A RegisterName: DMAC_CTRLAx [x = 0..3]Access: Read/WriteRes

3276264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A•SRC_WIDTH•DST_WIDTH•DONE0: The transfer is performed.1: If SOD field of DMAC_CFG register is set to

3286264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.17 DMAC Channel x [x = 0..3] Control B RegisterName: DMAC_CTRLBx [x = 0..3]Access: Read/WriteRes

3296264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• DST_DSCR0: Destination address is updated when the descriptor is fetched from the memory.1: Buffer

336264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A10. Peripherals10.1 User InterfaceThe peripherals are mapped in the upper 256 Mbytes of the address sp

3306264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.18 DMAC Channel x [x = 0..3] Configuration RegisterName: DMAC_CFGx [x = 0..3]Access: Read/WriteR

3316264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A0: AHB Bus Locking capability is disabled.1: AHB Bus Locking capability is enabled.•LOCK_IF_L0: The M

3326264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.19 DMAC Channel x [x = 0..3] Source Picture in Picture Configuration RegisterName: DMAC_SPIPx [x

3336264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A26.5.20 DMAC Channel x [x = 0..3] Destination Picture in Picture Configuration RegisterName: DMAC_DPI

3346264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

3356264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A27. Peripheral DMA Controller (PDC)27.1 DescriptionThe Peripheral DMA Controller (PDC) transfers data

3366264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A27.2 Block DiagramFigure 27-1. Block DiagramPDCFULL DUPLEXPERIPHERALTHRRHRPDC Channel APDC Channel BC

3376264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A27.3 Functional Description27.3.1 ConfigurationThe PDC channel user interface enables the user to con

3386264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe following list gives an overview of how status register flags behave depending on thecounters’ va

3396264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A27.3.5.4 Transmit Buffer EmptyThis flag is set when PERIPH_TCR register reaches zero with PERIPH_TNCR

346264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A10.2.1 Peripheral Interrupts and Clock Control10.2.1.1 System InterruptThe System Interrupt in Source

3406264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A27.4 Peripheral DMA Controller (PDC) User InterfaceNote: 1. PERIPH: Ten registers are mapped in the p

3416264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A27.4.1 Receive Pointer RegisterRegister Name: PERIPH_RPRAccess Type: Read/Write• RXPTR: Receive Point

3426264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A27.4.2 Receive Counter RegisterRegister Name: PERIPH_RCRAccess Type: Read/Write• RXCTR: Receive Count

3436264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A27.4.3 Transmit Pointer RegisterRegister Name: PERIPH_TPRAccess Type: Read/Write• TXPTR: Transmit Cou

3446264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A27.4.5 Receive Next Pointer RegisterRegister Name: PERIPH_RNPRAccess Type: Read/Write• RXNPTR: Receiv

3456264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A27.4.7 Transmit Next Pointer RegisterRegister Name: PERIPH_TNPRAccess Type: Read/Write• TXNPTR: Trans

3466264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A27.4.9 Transfer Control RegisterRegister Name: PERIPH_PTCRAccess Type: Write• RXTEN: Receiver Transfe

3476264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A27.4.10 Transfer Status RegisterRegister Name: PERIPH_PTSRAccess Type: Read• RXTEN: Receiver Transfer

3486264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

3496264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A28. Clock Generator28.1 DescriptionThe Clock Generator is made up of 2 PLLs, a Main Oscillator, and a

356264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A10.3 Peripherals Signals Multiplexing on I/O LinesThe AT91CAP9S500A/AT91CAP9S250A features 4 PIO contr

3506264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 28-2. Main Oscillator Block Diagram 28.3.1 Main Oscillator ConnectionsThe Clock Generator inte

3516264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AWhen disabling the main oscillator by clearing the MOSCEN bit in CKGR_MOR, the MOSCS bitin PMC_SR is

3526264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 28-4. Divider and PLL Block Diagram28.4.1 PLL FilterThe PLL requires connection to an external

3536264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe PLL allows multiplication of the divider’s outputs. The PLL clock signal has a frequency thatdepe

3546264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29. Power Management Controller (PMC)29.1 DescriptionThe Power Management Controller (PMC) optimizes

3556264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 29-1. Master Clock Controller29.3 Processor Clock ControllerThe PMC features a Processor Clock

3566264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.5 Peripheral Clock ControllerThe Power Management Controller controls the clocks of each embedded

3576264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ASo, the main oscillator will be enabled (MOSCS bit set) after 56 Slow Clock Cycles.2. Checking the Ma

3586264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe OUTB field is used to select the PLL B output frequency range.The MULB field is the PLL B multipl

3596264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A– Program the PRES field in the PMC_MCKR register.– Wait for the MCKRDY bit to be set in the PMC_SR r

366264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A10.3.1 PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller APIO Controller A Appl

3606264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AOnce the PMC_PCKx register has been programmed, The corresponding programmableclock must be enabled a

3616264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AWhen the prescaler is activated, an additional time of 64 clock cycles of the new selected clockhas t

3626264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.8.2 Clock Switching WaveformsFigure 29-3. Switch Master Clock from Slow Clock to PLL Clock Figure

3636264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 29-5. Change PLLA Programming Figure 29-6. Change PLLB ProgrammingSlow ClockSlow ClockPLLA Clo

3646264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 29-7. Programmable Clock Output Programming PLL ClockPCKRDYPCKx OutputWrite PMC_PCKxWrite PMC_

3656264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.9 Power Management Controller (PMC) User Interface Table 29-3. Register Mapping Offset Register N

3666264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.9.1 PMC System Clock Enable RegisterRegister Name: PMC_SCERAccess Type: Write-only • UHP: USB Host

3676264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.9.2 PMC System Clock Disable Register Register Name: PMC_SCDRAccess Type: Write-only • PCK: Proce

3686264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.9.3 PMC System Clock Status Register Register Name: PMC_SCSRAccess Type: Read-only • PCK: Processo

3696264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.9.4 PMC Peripheral Clock Enable RegisterRegister Name: PMC_PCERAccess Type: Write-only • PIDx: Per

376264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A10.3.2 PIO Controller B MultiplexingTable 10-3. Multiplexing on PIO Controller BPIO Controller B Appli

3706264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.9.6 PMC Peripheral Clock Status RegisterRegister Name: PMC_PCSRAccess Type: Read-only • PIDx: Peri

3716264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.9.7 PMC UTMI Clock Configuration RegisterRegister Name: CKGR_UCKRAccess Type: Read/Write • UPLLEN:

3726264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.9.8 PMC Clock Generator Main Oscillator RegisterRegister Name: CKGR_MORAccess Type: Read/Write • M

3736264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.9.9 PMC Clock Generator Main Clock Frequency Register Register Name: CKGR_MCFRAccess Type: Read-on

3746264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.9.10 PMC Clock Generator PLL A Register Register Name: CKGR_PLLARAccess Type: Read/Write Possible

3756264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.9.11 PMC Clock Generator PLL B Register Register Name: CKGR_PLLBRAccess Type: Read/Write Possible

3766264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.9.12 PMC Master Clock RegisterRegister Name: PMC_MCKRAccess Type: Read/Write • CSS: Master Clock S

3776264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AAccess Type: Read/Write • CSS: Master Clock Selection • PRES: Programmable Clock Prescaler 31 30 29

3786264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.9.14 PMC Interrupt Enable RegisterRegister Name: PMC_IERAccess Type: Write-only • MOSCS: Main Osci

3796264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.9.15 PMC Interrupt Disable RegisterRegister Name: PMC_IDRAccess Type: Write-only • MOSCS: Main Osc

386264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A10.3.3 PIO Controller C MultiplexingTable 10-4. Multiplexing on PIO Controller CPIO Controller C Appli

3806264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.9.16 PMC Status RegisterRegister Name: PMC_SRAccess Type: Read-only • MOSCS: MOSCS Flag Status0 =

3816264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A29.9.17 PMC Interrupt Mask RegisterRegister Name: PMC_IMRAccess Type: Read-only • MOSCS: Main Oscill

3826264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

3836264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30. Advanced Interrupt Controller (AIC)30.1 DescriptionThe Advanced Interrupt Controller (AIC) is an

3846264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30.2 Block DiagramFigure 30-1. Block Diagram30.3 Application Block DiagramFigure 30-2. Description of

3856264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30.5 I/O Line Description 30.6 Product Dependencies30.6.1 I/O LinesThe interrupt signals FIQ and IRQ0

3866264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30.7 Functional Description30.7.1 Interrupt Source Control30.7.1.1 Interrupt Source ModeThe Advanced

3876264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30.7.1.5 Internal Interrupt Source Input StageFigure 30-4. Internal Interrupt Source Input Stage30.7

3886264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30.7.2 Interrupt LatenciesGlobal interrupt latencies depend on several parameters, including:• The ti

3896264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30.7.2.3 Internal Interrupt Edge Triggered SourceFigure 30-8. Internal Interrupt Edge Triggered Sour

396264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A10.3.4 PIO Controller D Multiplexing Table 10-5. Multiplexing on PIO Controller DPIO Controller D Appl

3906264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source witha high

3916264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AIt is assumed that:1. The Advanced Interrupt Controller has been programmed, AIC_SVR registers are lo

3926264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Abeing executed before, and of loading the CPSR with the stored SPSR, masking or unmasking the interru

3936264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A1. The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link

3946264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt PendingRegister (A

3956264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A(arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including thevalue

3966264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30.8 Advanced Interrupt Controller (AIC) User Interface30.8.1 Base Address The AIC is mapped at the a

3976264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30.8.3 AIC Source Mode RegisterRegister Name: AIC_SMR0..AIC_SMR31Access Type: Read/WriteReset Value:

3986264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30.8.4 AIC Source Vector RegisterRegister Name: AIC_SVR0..AIC_SVR31Access Type: Read/WriteReset Valu

3996264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30.8.6 AIC FIQ Vector RegisterRegister Name: AIC_FVRAccess Type: Read-onlyReset Value: 0x0 • FIQV: FI

46264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A2. AT91CAP9S500A/AT91CAP9S250A Block Diagram Figure 2-1. AT91CAP9S500A/AT91CAP9S250A Block DiagramARM92

406264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A10.4 Embedded Peripherals 10.4.1 Serial Peripheral Interface• Supports communication with serial exter

4006264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30.8.8 AIC Interrupt Pending RegisterRegister Name: AIC_IPRAccess Type: Read-onlyReset Value: 0x0 •

4016264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30.8.10 AIC Core Interrupt Status RegisterRegister Name: AIC_CISRAccess Type: Read-onlyReset Value: 0

4026264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30.8.12 AIC Interrupt Disable Command RegisterRegister Name: AIC_IDCRAccess Type: Write-only • FIQ, S

4036264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30.8.14 AIC Interrupt Set Command RegisterRegister Name: AIC_ISCRAccess Type: Write-only • FIQ, SYS,

4046264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30.8.16 AIC Spurious Interrupt Vector RegisterRegister Name: AIC_SPUAccess Type: Read/WriteReset Valu

4056264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30.8.18 AIC Fast Forcing Enable RegisterRegister Name: AIC_FFERAccess Type: Write-only • SYS, PID2-PI

4066264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A30.8.20 AIC Fast Forcing Status RegisterRegister Name: AIC_FFSRAccess Type: Read-only • SYS, PID2-PID

4076264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A31. Debug Unit (DBGU)31.1 DescriptionThe Debug Unit provides a single entry point from the processor

4086264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A31.2 Block DiagramFigure 31-1. Debug Unit Functional Block DiagramFigure 31-2. Debug Unit Application

4096264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A31.3 Product Dependencies31.3.1 I/O LinesDepending on product integration, the Debug Unit pins may be

416264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• IrDA modulation and demodulation– Communication at up to 115.2 Kbps• Test Modes– Remote Loopback, Lo

4106264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 31-3. Baud Rate Generator31.4.2 Receiver31.4.2.1 Receiver Reset, Enable and DisableAfter devic

4116264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 31-4. Start Bit DetectionFigure 31-5. Character Reception31.4.2.3 Receiver ReadyWhen a complet

4126264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Abit. If different, the parity error bit PARE in DBGU_SR is set at the same time the RXRDY is set.The

4136264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250APARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When aparity bi

4146264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read ofthe da

4156264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe Debug Communication Channel contains two registers that are accessible through the ICEBreaker on

4166264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A31.5 Debug Unit User Interface Table 31-2. Debug Unit Memory MapOffset Register Name Access Reset Va

4176264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A31.5.1 Debug Unit Control RegisterName: DBGU_CRAccess Type: Write-only • RSTRX: Reset Receiver0 = N

4186264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A31.5.2 Debug Unit Mode RegisterName: DBGU_MRAccess Type: Read/Write • PAR: Parity Type • CHMODE: Ch

4196264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A31.5.3 Debug Unit Interrupt Enable RegisterName: DBGU_IERAccess Type: Write-only• RXRDY: Enable RXR

426264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A10.4.7 Pulse Width Modulation Controller• 4 channels, one 16-bit counter per channel• Common clock gen

4206264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A31.5.4 Debug Unit Interrupt Disable RegisterName: DBGU_IDRAccess Type: Write-only • RXRDY: Disable

4216264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A31.5.5 Debug Unit Interrupt Mask RegisterName: DBGU_IMRAccess Type: Read-only• RXRDY: Mask RXRDY In

4226264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A31.5.6 Debug Unit Status RegisterName: DBGU_SRAccess Type: Read-only • RXRDY: Receiver Ready0 = No

4236264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• TXBUFE: Transmission Buffer Empty0 = The buffer empty signal from the transmitter PDC channel is in

4246264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A31.5.7 Debug Unit Receiver Holding RegisterName: DBGU_RHRAccess Type: Read-only • RXCHR: Received C

4256264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A31.5.9 Debug Unit Baud Rate Generator RegisterName: DBGU_BRGRAccess Type: Read/Write • CD: Clock Di

4266264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A31.5.10 Debug Unit Chip ID RegisterName: DBGU_CIDRAccess Type: Read-only • VERSION: Version of the De

4276264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• NVPSIZ2 Second Nonvolatile Program Memory Size • SRAMSIZ: Internal SRAM SizeNVPSIZ2 Size0000None000

4286264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• ARCH: Architecture Identifier • NVPTYP: Nonvolatile Program Memory Type• EXT: Extension Flag0 = Chi

4296264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A31.5.11 Debug Unit Chip ID Extension RegisterName: DBGU_EXIDAccess Type: Read-only • EXID: Chip ID

436264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A10.4.10 USB Host Port• Compliance with OHCI Rev 1.0 Specification• Compliance with USB V2.0 Full-speed

4306264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

4316264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32. Parallel Input/Output Controller (PIO)32.1 DescriptionThe Parallel Input/Output Controller (PIO)

4326264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.2 Block DiagramFigure 32-1. Block DiagramFigure 32-2. Application Block DiagramEmbedded Peripheral

4336264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.3 Product Dependencies32.3.1 Pin MultiplexingEach pin is configurable, according to product defini

4346264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.4 Functional DescriptionThe PIO Controller features up to 32 fully-programmable I/O lines. Most of

4356264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.4.1 Pull-up Resistor ControlEach I/O line is designed with an embedded pull-up resistor. The pull-

4366264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe results of these write operations are detected in PIO_OSR (Output Status Register). Whena bit in

4376264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 32-4. Output Line Timings 32.4.8 InputsThe level on each I/O line can be read through PIO_PDSR

4386264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 32-5. Input Glitch Filter Timing 32.4.10 Input Change InterruptThe PIO Controller can be progr

4396264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-u

446264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• Full- and half-duplex operations• MII or RMII interface to the physical layer• Register Interface to

4406264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Awriting to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not mul

4416264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ANotes: 1. Reset value of PIO_PSR depends on the product implementation.2. PIO_ODSR is Read-only or Re

4426264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.6.1 PIO Controller PIO Enable RegisterName: PIO_PERAccess Type: Write-only • P0-P31: PIO Enable0 =

4436264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.6.3 PIO Controller PIO Status RegisterName: PIO_PSRAccess Type: Read-only • P0-P31: PIO Status0 =

4446264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.6.5 PIO Controller Output Disable RegisterName: PIO_ODRAccess Type: Write-only • P0-P31: Output Di

4456264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.6.7 PIO Controller Input Filter Enable RegisterName: PIO_IFERAccess Type: Write-only • P0-P31: Inp

4466264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.6.9 PIO Controller Input Filter Status RegisterName: PIO_IFSRAccess Type: Read-only • P0-P31: Inpu

4476264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.6.11 PIO Controller Clear Output Data RegisterName: PIO_CODRAccess Type: Write-only • P0-P31: Set

4486264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.6.13 PIO Controller Pin Data Status RegisterName: PIO_PDSRAccess Type: Read-only • P0-P31: Output

4496264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.6.15 PIO Controller Interrupt Disable RegisterName: PIO_IDRAccess Type: Write-only • P0-P31: Input

456264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A11. Metal Programmable BlockThe Metal Programmable Block (MPBlock) is connected to internal resources

4506264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.6.17 PIO Controller Interrupt Status RegisterName: PIO_ISRAccess Type: Read-only • P0-P31: Input C

4516264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.6.19 PIO Multi-driver Disable RegisterName: PIO_MDDRAccess Type: Write-only • P0-P31: Multi Drive

4526264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.6.21 PIO Pull Up Disable RegisterName: PIO_PUDRAccess Type: Write-only • P0-P31: Pull Up Disable.0

4536264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.6.23 PIO Pull Up Status RegisterName: PIO_PUSRAccess Type: Read-only • P0-P31: Pull Up Status.0 =

4546264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.6.25 PIO Peripheral B Select RegisterName: PIO_BSRAccess Type: Write-only • P0-P31: Peripheral B S

4556264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.6.27 PIO Output Write Enable RegisterName: PIO_OWERAccess Type: Write-only • P0-P31: Output Write

4566264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A32.6.29 PIO Output Write Status RegisterName: PIO_OWSRAccess Type: Read-only • P0-P31: Output Write S

4576264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33. Serial Peripheral Interface (SPI)33.1 DescriptionThe Serial Peripheral Interface (SPI) circuit is

4586264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.2 Block DiagramFigure 33-1. Block Diagram 33.3 Application Block Diagram Figure 33-2. Application

4596264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.4 Signal Description 33.5 Product Dependencies33.5.1 I/O LinesThe pins used for interfacing the c

466264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• 30 or 60 MHz UTMI+ USB Clock• MCK System Clock• DDRCK Dual Rate System Clock• PCK Processor Clock• 5

4606264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Afour possible combinations that are incompatible with one another. Thus, a master/slave pairmust use

4616264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 33-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)*SPCK(CPOL = 0)SPCK(CPOL = 1)1 2345

4626264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.6.3 Master Mode OperationsWhen configured in Master Mode, the SPI operates on the clock generated

4636264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.6.3.1 Master Mode Block DiagramFigure 33-5. Master Mode Block DiagramShift RegisterSPCKMOSILSB MSB

4646264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.6.3.2 Master Mode Flow Diagram Figure 33-6. Master Mode Flow Diagram SPI EnableCSAAT ?PS ?10011NPC

4656264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.6.3.3 Clock GenerationThe SPI Baud rate clock is generated by dividing the Master Clock (MCK) , by

4666264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• Fixed Peripheral Select: SPI exchanges data with only one peripheral• Variable Peripheral Select: D

4676264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ATo facilitate interfacing with such devices, the Chip Select Register can be programmed withthe CSAAT

4686264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.6.4 SPI Slave ModeWhen operating in Slave Mode, the SPI processes data bits on the clock provided

4696264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 33-9. Slave Mode Functional Block Diagram Shift RegisterSPCKSPIENSLSB MSBNSSMOSISPI_RDRRDSPI C

476264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A11.2 External ConnectivityThe MPBlock is connected to the following external resources.11.2.1 Dedicate

4706264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.7 Serial Peripheral Interface (SPI) User Interface Table 33-3. SPI Register MappingOffset Registe

4716264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.7.1 SPI Control RegisterName: SPI_CRAccess Type: Write-only• SPIEN: SPI Enable0 = No effect.1 = En

4726264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.7.2 SPI Mode RegisterName: SPI_MRAccess Type: Read/Write • MSTR: Master/Slave Mode0 = SPI is in Sl

4736264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AIf PCSDEC = 1:NPCS[3:0] output signals = PCS.• DLYBCS: Delay Between Chip SelectsThis field defines t

4746264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.7.3 SPI Receive Data RegisterName: SPI_RDRAccess Type: Read-only • RD: Receive DataData received

4756264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.7.4 SPI Transmit Data RegisterName: SPI_TDR Access Type: Write-only• TD: Transmit DataData to be t

4766264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.7.5 SPI Status RegisterName: SPI_SRAccess Type: Read-only • RDRF: Receive Data Register Full0 = N

4776264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A0 = As soon as data is written in SPI_TDR.1 = SPI_TDR and internal shifter are empty. If a transfer d

4786264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.7.6 SPI Interrupt Enable RegisterName: SPI_IERAccess Type: Write-only • RDRF: Receive Data Registe

4796264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.7.7 SPI Interrupt Disable RegisterName: SPI_IDRAccess Type: Write-only • RDRF: Receive Data Regist

486264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 11-2. Typical Prototyping Solution Bus Matrix4-channelDMAEBIMetal Programmable Block500K Gates

4806264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.7.8 SPI Interrupt Mask RegisterName: SPI_IMRAccess Type: Read-only • RDRF: Receive Data Register

4816264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A33.7.9 SPI Chip Select RegisterName: SPI_CSR0... SPI_CSR3Access Type: Read/Write • CPOL: Clock Polar

4826264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• SCBR: Serial Clock Baud RateIn Master Mode, the SPI Interface uses a modulus counter to derive the

4836264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34. Two-wire Interface (TWI)34.1 DescriptionThe Atmel Two-wire Interface (TWI) interconnects componen

4846264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.2 List of Abbreviations34.3 Block DiagramFigure 34-1. Block DiagramTable 34-2. AbbreviationsAbbrev

4856264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.4 Application Block DiagramFigure 34-2. Application Block Diagram 34.4.1 I/O Lines Description34.5

4866264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.6 Functional Description34.6.1 Transfer FormatThe data put on the TWD line must be 8 bits long. Da

4876264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.7 Master Mode34.7.1 DefinitionThe Master is the device which starts a transfer, generates a clock

4886264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ATXRDY is used as Transmit Ready for the PDC transmit channel.Figure 34-6. Master Write with One Data

4896264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ARXRDY bit is set in the status register, a character has been received in the receive-holding reg-ist

496264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A12. ARM926EJ-S Processor Overview12.1 OverviewThe ARM926EJ-S processor is a member of the ARM9™ family

4906264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe three internal address bytes are configurable through the Master Mode register(TWI_MMR).If the sl

4916264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AExample: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10)1. Program

4926264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.7.7 Using the Peripheral DMA Controller (PDC)The use of the PDC significantly reduces the CPU load

4936264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.7.8 Read/Write FlowchartsThe following flowcharts shown in Figure 34-14, Figure 34-15 on page 494,

4946264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 34-15. TWI Write Operation with Single Data Byte and Internal AddressBEGINSet TWI clock(CLDIV,

4956264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 34-16. TWI Write Operation with Multiple Data Bytes with or without Internal AddressSet the Co

4966264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 34-17. TWI Read Operation with Single Data Byte without Internal AddressSet the Control regist

4976264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 34-18. TWI Read Operation with Single Data Byte and Internal AddressSet the Control register:-

4986264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 34-19. TWI Read Operation with Multiple Data Bytes with or without Internal AddressInternal ad

4996264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.8 Multi-master Mode34.8.1 DefinitionMore than one master may handle the bus at the same time witho

56264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A3. Signal DescriptionTable 3-1 gives details on the signal name classified by peripheral.Table 3-1. Sig

506264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A12.2 Block DiagramFigure 12-1. ARM926EJ-S Internal Functional Block Diagram12.3 ARM9EJ-S Processor12.3

5006264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A7. If TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode

5016264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 34-22. Multi-master FlowchartProgramm the SLAVE mode:SADR + MSDIS + SVENSVACC = 1 ?TXCOMP = 1

5026264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.9 Slave Mode34.9.1 DefinitionThe Slave Mode is defined as a mode where the device receives the clo

5036264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ANote that a STOP or a repeated START always follows a NACK.See Figure 34-24 on page 504. 34.9.4.2 Wri

5046264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 34-24. Read Access Ordered by a MASTERNotes: 1. When SVACC is low, the state of SVREAD becomes

5056264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.9.5.3 General CallThe general call is performed in order to change the address of the slave.If a G

5066264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.9.5.4 Clock SynchronizationIn both read and write modes, it may happen that TWI_THR/TWI_RHR buffer

5076264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.9.5.6 Clock Synchronization in Write ModeThe clock is tied low if the shift register and the TWI_R

5086264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.9.5.7 Reversal after a Repeated Start34.9.5.8 Reversal of Read to WriteThe master initiates the co

5096264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.9.6 Read Write FlowchartsThe flowchart shown in Figure 34-31 on page 509 gives an example of read

516264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• ARM state and Jazelle state using the BXJ instruction All exceptions are entered, handled and exited

5106264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.10 Two-wire Interface (TWI) User Interface Table 34-5. Two-wire Interface (TWI) User InterfaceOffs

5116264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.10.1 TWI Control RegisterName: TWI_CRAccess: Write-onlyReset Value: 0x00000000• START: Send a STAR

5126264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A1 = If SVDIS = 0, the slave mode is enabled.Note: Switching from Master to Slave mode is only permitt

5136264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.10.2 TWI Master Mode RegisterName: TWI_MMRAccess: Read/WriteReset Value: 0x00000000• IADRSZ: Inter

5146264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.10.3 TWI Slave Mode RegisterName: TWI_SMRAccess: Read/WriteReset Value: 0x00000000• SADR: Slave Ad

5156264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.10.4 TWI Internal Address RegisterName: TWI_IADRAccess: Read/WriteReset Value: 0x00000000• IADR: I

5166264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.10.5 TWI Clock Waveform Generator RegisterName: TWI_CWGRAccess: Read/WriteReset Value: 0x00000000T

5176264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.10.6 TWI Status RegisterName: TWI_SRAccess: Read-onlyReset Value: 0x0000F009• TXCOMP: Transmission

5186264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ATXRDY used in Slave mode:0 = As soon as data is written in the TWI_THR, until this data has been tran

5196264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A0 = Each data byte has been correctly received by the Master.1 = In read mode, a data byte has not be

526264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• Supervisor mode is a protected mode for the operating system• Abort mode is entered after a data or

5206264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.10.7 TWI Interrupt Enable RegisterName: TWI_IERAccess: Write-onlyReset Value: 0x00000000• TXCOMP:

5216264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.10.8 TWI Interrupt Disable RegisterName: TWI_IDRAccess: Write-onlyReset Value: 0x00000000• TXCOMP:

5226264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.10.9 TWI Interrupt Mask RegisterName: TWI_IMRAccess: Read-onlyReset Value: 0x00000000• TXCOMP: Tra

5236264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A34.10.10 TWI Receive Holding RegisterName: TWI_RHRAccess: Read-onlyReset Value: 0x00000000• RXDATA: M

5246264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

5256264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35. Universal Synchronous/Asynchronous Receiver/Transceiver35.1 DescriptionThe Universal Synchronous

5266264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.2 Block DiagramFigure 35-1. USART Block Diagram Peripheral DMAControllerChannel ChannelAICReceiver

5276264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.3 Application Block DiagramFigure 35-2. Application Block Diagram35.4 I/O Lines Description Table

5286264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.5 Product Dependencies35.5.1 I/O LinesThe pins used for interfacing the USART may be multiplexed w

5296264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.6 Functional DescriptionThe USART is capable of managing several types of serial synchronous or as

536264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Aregisters used to hold either data or address values. Register r14 is used as a Link register thathold

5306264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 35-3. Baud Rate Generator35.6.1.1 Baud Rate in Asynchronous Mode If the USART is programmed to

5316264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe baud rate is calculated with the following formula:The baud rate error is calculated with the fol

5326264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 35-4. Fractional Baud Rate Generator35.6.1.3 Baud Rate in Synchronous ModeIf the USART is prog

5336264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ADi is a binary value encoded on a 4-bit field, named DI, as represented in Table 35-3. Fi is a binary

5346264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 35-5. Elementary Time Unit (ETU)35.6.2 Receiver and Transmitter ControlAfter reset, the receiv

5356264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 35-6. Character Transmit The characters are sent by writing in the Transmit Holding Register (

5366264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 35-8. NRZ to Manchester EncodingThe Manchester encoded character can also be encapsulated by a

5376264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Aoccurs at the middle of the second bit time. Two distinct sync patterns are used: the commandsync and

5386264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 35-11. Bit Resynchronization35.6.3.3 Asynchronous ReceiverIf the USART is programmed in asynch

5396264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 35-12. Asynchronous Start Detection Figure 35-13. Asynchronous Character Reception35.6.3.4 Man

546264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 12-2. Status Register Format Figure 12-2 shows the status register format, where:• N: Negative,

5406264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 35-14. Asynchronous Start Bit DetectionThe receiver is activated and starts Preamble and Frame

5416264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Afield in the US_RHR register and the RXSYNH is updated. RXCHR is set to 1 when the receivedcharacter

5426264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Aswitches to receiving mode. The demodulated stream is sent to the Manchester decoder.Because of bit c

5436264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.6.3.7 Receiver OperationsWhen a character reception is completed, it is transferred to the Receive

5446264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.6.3.8 ParityThe USART supports five parity modes selected by programming the PAR field in the Mode

5456264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 35-22. Parity Error35.6.3.9 Multidrop ModeIf the PAR field in the Mode Register (US_MR) is pro

5466264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 35-23. Timeguard OperationsTable 35-7 indicates the maximum length of a timeguard period that

5476264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Aon RXD before a new character is received will not provide a time-out. This prevents having to handle

5486264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.6.3.12 Framing ErrorThe receiver is capable of detecting framing errors. A framing error happens w

5496264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRKcommands a

556264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive.There is one exception i

5506264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 35-27. Connection with a Remote Device for Hardware HandshakingSetting the USART to operate wi

5516264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.6.4 ISO7816 ModeThe USART features an ISO7816-compatible operating mode. This mode permits interfa

5526264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AIf a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, ass

5536264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AWhen the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in theChannel Status

5546264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.6.5.1 IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation schem

5556264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.6.5.3 IrDA DemodulatorThe demodulator is based on the IrDA Receive filter comprised of an 8-bit do

5566264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.6.6 RS485 ModeThe USART features the RS485 mode to enable line driver control. While operating in

5576264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.6.7 Test ModesThe USART can be programmed to operate in three different test modes. The internal l

5586264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.6.7.4 Remote Loopback ModeRemote loopback mode directly connects the RXD pin to the TXD pin, as sh

5596264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.7 USART User Interface Table 35-11. USART Memory Map Offset Register Name Access Reset State0x000

566264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• Data processing instructions• Status register transfer instructions• Load and Store instructions• Co

5606264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.7.1 USART Control RegisterName: US_CRAccess Type: Write-only • RSTRX: Reset Receiver0: No effect.1

5616264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Regis

5626264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.7.2 USART Mode RegisterName: US_MRAccess Type: Read/Write • USART_MODE • USCLKS: Clock Selection

5636264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• CHRL: Character Length • SYNC: Synchronous Mode Select0: USART operates in Asynchronous Mode.1: US

5646264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A0: CHRL defines character length.1: 9-bit character length.• CLKO: Clock Output Select0: The USART do

5656264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.7.3 USART Interrupt Enable RegisterName: US_IERAccess Type: Write-only• RXRDY: RXRDY Interrupt En

5666264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.7.4 USART Interrupt Disable RegisterName: US_IDRAccess Type: Write-only • RXRDY: RXRDY Interrupt D

5676264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.7.5 USART Interrupt Mask RegisterName: US_IMRAccess Type: Read-only• RXRDY: RXRDY Interrupt Mask•

5686264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.7.6 USART Channel Status RegisterName: US_CSRAccess Type: Read-only • RXRDY: Receiver Ready0: No c

5696264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• PARE: Parity Error0: No parity error has been detected since the last RSTSTA.1: At least one parity

576264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A12.3.9 New ARM Instruction Set.Notes: 1. A Thumb BLX contains two consecutive Thumb instructions, and

5706264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.7.7 USART Receive Holding RegisterName: US_RHRAccess Type: Read-only • RXCHR: Received CharacterLa

5716264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.7.8 USART Transmit Holding RegisterName: US_THRAccess Type: Write-only • TXCHR: Character to be Tr

5726264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.7.9 USART Baud Rate Generator RegisterName: US_BRGRAccess Type: Read/Write • CD: Clock Divider • F

5736264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.7.10 USART Receiver Time-out RegisterName: US_RTORAccess Type: Read/Write • TO: Time-out Value0: T

5746264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.7.11 USART Transmitter Timeguard RegisterName: US_TTGRAccess Type: Read/Write • TG: Timeguard Valu

5756264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.7.12 USART FI DI RATIO RegisterName: US_FIDIAccess Type: Read/WriteReset Value : 0x174 • FI_DI_RAT

5766264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.7.14 USART Manchester Configuration RegisterName: US_MANAccess Type: Read/Write• TX_PL: Transmitte

5776264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.•

5786264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A35.7.15 USART IrDA FILTER RegisterName: US_IFAccess Type: Read/Write• IRDA_FILTER: IrDA FilterSets th

5796264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36. Serial Synchronous Controller (SSC)36.1 DescriptionThe Atmel Synchronous Serial Controller (SSC)

586264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A12.4 CP15 CoprocessorCoprocessor 15, or System Control Coprocessor CP15, is used to configure and cont

5806264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.2 Block DiagramFigure 36-1. Block Diagram36.3 Application Block DiagramFigure 36-2. Application Bl

5816264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.4 Pin Name List36.5 Product Dependencies36.5.1 I/O LinesThe pins used for interfacing the complian

5826264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 36-3. SSC Functional Block Diagram36.6.1 Clock ManagementThe transmitter clock can be generate

5836264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.6.1.1 Clock DividerFigure 36-4. Divided Clock Block Diagram The Master Clock divider is determine

5846264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A(CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredict-able r

5856264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.6.1.4 Serial Clock Ratio ConsiderationsThe Transmitter and the Receiver can be programmed to opera

5866264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.6.3 Receiver OperationsA received frame is triggered by a start event and can be followed by synch

5876264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AA start can be programmed in the same manner on either side of the Transmit/Receive ClockRegister (RC

5886264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.6.5 Frame SyncThe Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to genera

5896264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.6.6.1 Compare FunctionsLength of the comparison patterns (Compare 0, Compare 1) and thus the numbe

596264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ANotes: 1. Register locations 0,5, and 13 each provide access to more than one register. The register a

5906264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 36-13. Transmit and Receive Frame Format in Edge/Pulse Start ModesNote: 1. Example of input on

5916264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 36-14. Transmit Frame Format in Continuous Mode Note: 1. STTDLY is set to 0. In this example,

5926264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 36-16. Interrupt Block Diagram36.7 SSC Application ExamplesThe SSC can support several serial

5936264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 36-18. Codec Application Block DiagramFigure 36-19. Time Slot Application Block DiagramSSCRKRF

5946264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.8 Synchronous Serial Controller (SSC) User InterfaceTable 36-4. Register MappingOffset Register Re

5956264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.8.1 SSC Control RegisterName: SSC_CRAccess Type: Write-only • RXEN: Receive Enable0: No effect.1:

5966264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.8.2 SSC Clock Mode RegisterName: SSC_CMRAccess Type: Read/Write • DIV: Clock Divider0: The Clock D

5976264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.8.3 SSC Receive Clock Mode RegisterName: SSC_RCMRAccess Type: Read/Write • CKS: Receive Clock Sele

5986264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• CKG: Receive Clock Gating Selection• START: Receive Start Selection • STOP: Receive Stop Selection0

5996264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.8.4 SSC Receive Frame Mode RegisterName: SSC_RFMRAccess Type: Read/Write • DATLEN: Data Length0: F

66264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AICE and JTAGNTRST Test Reset Signal Input Low No pull-up resistorTCK Test Clock Input No pull-up resist

606264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A12.4.1 CP15 Registers AccessCP15 registers can only be accessed in privileged mode by:• MCR (Move to C

6006264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• FSOS: Receive Frame Sync Output Selection• FSEDGE: Frame Sync Edge DetectionDetermines which edge o

6016264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.8.5 SSC Transmit Clock Mode RegisterName: SSC_TCMRAccess Type: Read/Write • CKS: Transmit Clock Se

6026264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• CKG: Transmit Clock Gating Selection • START: Transmit Start Selection • STTDLY: Transmit Start D

6036264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.8.6 SSC Transmit Frame Mode RegisterName: SSC_TFMRAccess Type: Read/Write • DATLEN: Data Length0:

6046264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• FSOS: Transmit Frame Sync Output Selection • FSDEN: Frame Sync Data Enable0: The TD line is driven

6056264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.8.7 SSC Receive Holding RegisterName: SSC_RHRAccess Type: Read-only • RDAT: Receive DataRight ali

6066264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.8.9 SSC Receive Synchronization Holding RegisterName: SSC_RSHRAccess Type: Read-only • RSDAT: Rec

6076264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.8.11 SSC Receive Compare 0 RegisterName: SSC_RC0RAccess Type: Read/Write • CP0: Receive Compare D

6086264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.8.12 SSC Receive Compare 1 RegisterName: SSC_RC1RAccess Type: Read/Write • CP1: Receive Compare D

6096264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.8.13 SSC Status RegisterName: SSC_SRAccess Type: Read-only • TXRDY: Transmit Ready0: Data has been

616264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A12.5 Memory Management Unit (MMU)The ARM926EJ-S processor implements an enhanced ARM architecture v5 M

6106264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A•CP0: Compare 00: A compare 0 has not occurred since the last read of the Status Register.1: A compar

6116264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.8.14 SSC Interrupt Enable RegisterName: SSC_IERAccess Type: Write-only • TXRDY: Transmit Ready Int

6126264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• CP0: Compare 0 Interrupt Enable0: No effect.1: Enables the Compare 0 Interrupt.• CP1: Compare 1 Int

6136264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.8.15 SSC Interrupt Disable RegisterName: SSC_IDRAccess Type: Write-only • TXRDY: Transmit Ready In

6146264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• CP0: Compare 0 Interrupt Disable0: No effect.1: Disables the Compare 0 Interrupt.• CP1: Compare 1 I

6156264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A36.8.16 SSC Interrupt Mask RegisterName: SSC_IMRAccess Type: Read-only • TXRDY: Transmit Ready Interr

6166264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• CP0: Compare 0 Interrupt Mask0: The Compare 0 Interrupt is disabled.1: The Compare 0 Interrupt is e

6176264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37. AC’97 Controller (AC’97C)37.1 DescriptionThe AC‘97 Controller is the hardware implementation of t

6186264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.2 Block DiagramFigure 37-1. Functional Block DiagramAC97 Channel AAC97C_CATHRAC97C_CARHRSlot #3...

6196264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.3 Pin Name List The AC‘97 reset signal provided to the primary codec can be generated by a PIO.37.

626264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A12.5.2 Translation Look-aside Buffer (TLB)The Translation Look-aside Buffer (TLB) caches translated en

6206264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.5 Product Dependencies37.5.1 I/O LinesThe pins used for interfacing the compliant external devices

6216264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.6 Functional Description37.6.1 Protocol overviewAC-link protocol is a bidirectional, fixed clock r

6226264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.6.1.1 Slot DescriptionTag SlotThe tag slot, or slot 0, is a 16-bit wide slot that always goes at t

6236264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.6.2 AC‘97 Controller Channel OrganizationThe AC’97 Controller features a Codec channel and 3 logic

6246264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.6.2.1 AC97 Controller SetupThe following operations must be performed in order to bring the AC’97

6256264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 37-5. Audio Transfer (PCM L Front, PCM R Front) on Channel x The TXEMPTY flag in the AC’97 Con

6266264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe application can also wait for an interrupt notice in order to read data fromAC97C_CxRHR. The inte

6276264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Aread AC’97 Controller Channel x Status Register (AC97C_CxSR), x being the channel whoseevent triggers

6286264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AData emitted on related slot: data[19:0] = {0x000, Byte1[1:0], Byte0[7:0]}.To Receive Word transfersD

6296264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Aframe and then determines which SLOTREQ bits to set active (low). These bits are passedfrom the AC97

636264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AA new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonlyknown as wrap

6306264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThis feature is implemented in AC97 modem codecs that need to report events such as Caller-ID and wak

6316264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• Wait for at least 1us• Clear WRST in the AC97C_MR register.The application can check that operation

6326264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.7 AC’97 Controller (AC97C) User InterfaceTable 37-4. Register MappingOffset Register Register Name

6336264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.7.1 AC’97 Controller Mode RegisterName: AC97C_MRAccess Type: Read-Write • VRA: Variable Rate (for

6346264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.7.2 AC’97 Controller Input Channel Assignment RegisterRegister Name: AC97C_ICAAccess Type: Read/Wr

6356264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.7.4 AC’97 Controller Codec Channel Receive Holding RegisterRegister Name: AC97C_CORHRAccess Type:

6366264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.7.6 AC’97 Controller Channel A, Channel B, Channel C Receive Holding RegisterRegister Name: AC97C_

6376264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.7.8 AC’97 Controller Channel A Status RegisterRegister Name: AC97C_CASRAccess Type: Read-only 37.7

6386264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.7.11 AC’97 Controller Codec Channel Status RegisterRegister Name: AC97C_COSRAccess Type: Read-onl

6396264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.7.12 AC’97 Controller Channel A Mode RegisterRegister Name: AC97C_CAMRAccess Type: Read/Write 37.7

646264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe DCache contains an eight data word entry, single address entry write-back buffer used tohold write

6406264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.7.14 AC’97 Controller Channel C Mode RegisterRegister Name: AC97C_CCMRAccess Type: Read/Write• CEM

6416264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.7.15 AC’97 Controller Codec Channel Mode RegisterRegister Name: AC97C_COMRAccess Type: Read/Write•

6426264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.7.16 AC’97 Controller Status RegisterRegister Name: AC97C_SRAccess Type: Read-onlyWKUP and SOF fla

6436264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.7.17 AC’97 Controller Interrupt Enable RegisterRegister Name: AC97C_IERAccess Type: Write-only• SO

6446264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A37.7.19 AC’97 Controller Interrupt Mask RegisterRegister Name: AC97C_IMRAccess Type: Read-only• SOF:

6456264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

6466264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

6476264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38. Timer Counter (TC)38.1 DescriptionThe Timer Counter (TC) includes three identical 16-bit Timer Co

6486264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.2 Block DiagramFigure 38-1. Timer Counter Block Diagram Timer/Counter Channel 0Timer/Counter Chann

6496264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.3 Pin Name List38.4 Product Dependencies38.4.1 I/O Lines The pins used for interfacing the complia

656264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A12.7.2 Enabling and Disabling TCMsPrior to any enabling step, the user should configure the TCM sizes

6506264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.5 Functional Description38.5.1 TC DescriptionThe three channels of the Timer Counter are independe

6516264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 38-2. Clock Chaining SelectionFigure 38-3. Clock SelectionTimer/Counter Channel 0SYNCTC0XC0STI

6526264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.5.4 Clock ControlThe clock of each counter can be controlled in two different ways: it can be enab

6536264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR.• SYNC:

6546264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 38-5. Capture ModeTIMER_CLOCK1TIMER_CLOCK2TIMER_CLOCK3TIMER_CLOCK4TIMER_CLOCK5XC0XC1XC2TCCLKSC

6556264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.5.10 Waveform Operating ModeWaveform operating mode is entered by setting the WAVE parameter in TC

6566264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 38-6. Waveform ModeTCCLKSCLKIQSRSRQCLKSTA CLKEN CLKDISCPCDISBURSTTIOBRegister A Register B Reg

6576264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.5.11.1 WAVSEL = 00When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFF

6586264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 38-8. WAVSEL= 00 with trigger38.5.11.2 WAVSEL = 10When WAVSEL = 10, the value of TC_CV is incr

6596264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 38-10. WAVSEL = 10 With Trigger38.5.11.3 WAVSEL = 01When WAVSEL = 01, the value of TC_CV is in

666264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ATable 8 gives an overview of the supported transfers and different kinds of transactions they areused

6606264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 38-11. WAVSEL = 01 Without TriggerFigure 38-12. WAVSEL = 01 With Trigger38.5.11.4 WAVSEL = 11W

6616264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 38-13. WAVSEL = 11 Without Trigger Figure 38-14. WAVSEL = 11 With TriggerTimeCounter ValueRCRB

6626264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.5.12 External Event/Trigger ConditionsAn external event can be programmed to be detected on one of

6636264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.6 Timer Counter (TC) User Interface TC_BCR (Block Control Register) and TC_BMR (Block Mode Registe

6646264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.6.1 TC Block Control Register Register Name: TC_BCRAccess Type: Write-only• SYNC: Synchro Command0

6656264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.6.2 TC Block Mode Register Register Name: TC_BMRAccess Type: Read/Write • TC0XC0S: External Clock

6666264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.6.3 TC Channel Control Register Register Name: TC_CCRAccess Type: Write-only • CLKEN: Counter Cloc

6676264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.6.4 TC Channel Mode Register: Capture ModeRegister Name: TC_CMRAccess Type: Read/Write • TCCLKS: C

6686264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• ETRGEDG: External Trigger Edge Selection• ABETRG: TIOA or TIOB External Trigger Selection0 = TIOB i

6696264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.6.5 TC Channel Mode Register: Waveform ModeRegister Name: TC_CMRAccess Type: Read/Write • TCCLKS:

676264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A13. Debug and Test13.1 DescriptionThe AT91CAP9 features a number of complementary debug and test capab

6706264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• EEVTEDG: External Event Edge Selection• EEVT: External Event Selection Note: 1. If TIOB is chosen a

6716264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• ACPC: RC Compare Effect on TIOA • AEEVT: External Event Effect on TIOA• ASWTRG: Software Trigger Ef

6726264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• BEEVT: External Event Effect on TIOB • BSWTRG: Software Trigger Effect on TIOB BEEVT Effect0 0 none

6736264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.6.6 TC Counter Value Register Register Name: TC_CVAccess Type: Read-only • CV: Counter ValueCV con

6746264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.6.8 TC Register BRegister Name: TC_RBAccess Type: Read-only if WAVE = 0, Read/Write if WAVE = 1 •

6756264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.6.10 TC Status Register Register Name: TC_SRAccess Type: Read-only• COVFS: Counter Overflow Status

6766264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A1 = Clock is enabled.• MTIOA: TIOA Mirror0 = TIOA is low. If WAVE = 0, this means that TIOA pin is lo

6776264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.6.11 TC Interrupt Enable Register Register Name: TC_IERAccess Type: Write-only • COVFS: Counter Ov

6786264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.6.12 TC Interrupt Disable Register Register Name: TC_IDRAccess Type: Write-only • COVFS: Counter O

6796264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A38.6.13 TC Interrupt Mask Register Register Name: TC_IMRAccess Type: Read-only • COVFS: Counter Overf

686264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A13.2 Block DiagramFigure 13-1. Debug and Test Block DiagramICE-RTARM9EJ-SPDCDBGUPIODRXDDTXDTMSTCKTDIJT

6806264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

6816264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39. Controller Area Network (CAN)39.1 DescriptionThe CAN controller provides all the features require

6826264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.2 Block DiagramFigure 39-1. CAN Block DiagramInternal BusCAN InterruptCANRXController Area Network

6836264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.3 Application Block DiagramFigure 39-2. Application Block Diagram39.4 I/O Lines Description 39.5

6846264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.6 CAN Controller Features39.6.1 CAN Protocol OverviewThe Controller Area Network (CAN) is a multi-

6856264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 39-3. Message Acceptance ProcedureIf a mailbox is dedicated to receiving several messages (a f

6866264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.6.2.2 Receive MailboxWhen the CAN module receives a message, it looks for the first available mail

6876264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.6.3 Time Management UnitThe CAN Controller integrates a free-running 16-bit internal timer. The co

6886264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.6.4 CAN 2.0 Standard Features39.6.4.1 CAN Bit Timing ConfigurationAll controllers on a CAN bus mus

6896264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe SAMPLE POINT is the point in time at which the bus level is read and interpreted as thevalue of t

696264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A13.3 Application Examples13.3.1 Debug EnvironmentFigure 13-2 on page 69 shows a complete debug environ

6906264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ACAN baudrate= 500kbit/s => bit time= 2usDelay of the bus driver: 50 nsDelay of the receiver: 30nsD

6916264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ACAN Bus SynchronizationTwo types of synchronization are distinguished: “hard synchronization” at the

6926264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Afrozen. To go back to the standard mode, the ABM bit must be cleared in the CAN_MRregister.39.6.4.2 E

6936264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 39-7. Line Error ModeAn error active unit takes part in bus communication and sends an active

6946264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AReactive overload frames are automatically handled by the CAN controller even if the OVL bitin the CA

6956264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 39-8. Enabling Low-power Mode 39.6.5.2 Disabling Low-power ModeThe CAN controller can be awake

6966264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 39-9. Disabling Low-power Mode39.7 Functional Description39.7.1 CAN Controller InitializationA

6976264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 39-10. Possible Initialization Procedure39.7.2 CAN Controller Interrupt HandlingThere are two

6986264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A– Warn Limit interrupt: The CAN module is in Error-active Mode, but at least one of its error counter

6996264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.7.3 CAN Controller Message Handling39.7.3.1 Receive HandlingTwo modes are available to configure a

76264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ACompactFlash SupportCFCE1 - CFCE2 CompactFlash Chip Enable Output LowCFOE CompactFlash Output Enable Ou

706264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A13.4 Debug and Test Pin Description13.5 Functional Description13.5.1 Test PinOne dedicated pin, TST, i

7006264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AA mailbox is in Receive with Overwrite Mode once the MOT field in the CAN_MMRx registerhas been confi

7016264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AIf several mailboxes are chained to receive a buffer split into several messages, all mailboxesexcept

7026264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 39-14. Chaining Three Mailboxes to Receive a Buffer Split into Four Messages39.7.3.2 Transmiss

7036264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A0 and mailbox 5 have the same priority and have a message to send at the same time, thenthe message o

7046264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 39-16. Producer / Consumer ModelIn Pull Mode, a consumer transmits a remote frame to the produ

7056264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AAfter a remote frame has been received, the mailbox functions like a transmit mailbox. Themessage wit

7066264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 39-18. Consumer Handling39.7.4 CAN Controller Timing ModesUsing the free running 16-bit intern

7076264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.7.4.2 Time Triggered ModeIn Time Triggered Mode, basic cycles can be split into several time windo

7086264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Ais frozen. The TOVF bit in the CAN_SR register is cleared by reading the CAN_SR register.Depending on

7096264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8 Controller Area Network (CAN) User Interface Table 39-4. CAN Memory Map Offset Register Name Acc

716264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AARM9EJ-S Technical Reference Manual (DDI 0222A).13.5.3 JTAG Signal Description• TMS is the Test Mode S

7106264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8.1 CAN Mode RegisterName: CAN_MRAccess Type: Read/Write• CANEN: CAN Controller Enable0 = The CAN

7116264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8.2 CAN Interrupt Enable RegisterName: CAN_IERAccess Type: Write-only• MBx: Mailbox x Interrupt En

7126264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• SERR: Stuffing Error Interrupt Enable0 = No effect. 1 = Enable Stuffing Error interrupt.• AERR: Ack

7136264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8.3 CAN Interrupt Disable RegisterName: CAN_IDRAccess Type: Write-only• MBx: Mailbox x Interrupt D

7146264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• SERR: Stuffing Error Interrupt Disable0 = No effect. 1 = Disable Stuffing Error interrupt.• AERR: A

7156264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8.4 CAN Interrupt Mask RegisterName: CAN_IMRAccess Type: Read-only• MBx: Mailbox x Interrupt Mask0

7166264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• SERR: Stuffing Error Interrupt Mask0 = Bit Stuffing Error interrupt is disabled.1 = Bit Stuffing Er

7176264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8.5 CAN Status RegisterName: CAN_SRAccess Type: Read-only• MBx: Mailbox x Event0 = No event occurr

7186264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThis flag is automatically reset when Low power mode is disabled• WAKEUP: CAN controller is not in Lo

7196264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AA bit error is set when the bit value monitored on the line is different from the bit value sent.This

726264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AIt is not possible to switch directly between JTAG and ICE operations. A chip reset must beperformed a

7206264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8.6 CAN Baudrate RegisterName: CAN_BRAccess Type: Read/WriteAny modification on one of the fields

7216264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AAccess Type: Read-only• TIMERx: Timer This field represents the internal CAN controller 16-bit timer

7226264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8.8 CAN Timestamp RegisterName: CAN_TIMESTPAccess Type: Read-only• MTIMESTAMPx: Timestamp This fie

7236264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8.9 CAN Error Counter RegisterName: CAN_ECRAccess Type: Read-only • REC: Receive Error CounterWhen

7246264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8.10 CAN Transfer Command RegisterName: CAN_TCRAccess Type: Write-onlyThis register initializes se

7256264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8.11 CAN Abort Command RegisterName: CAN_ACRAccess Type: Write-onlyThis register initializes sever

7266264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8.12 CAN Message Mode RegisterName: CAN_MMRxAccess Type: Read/Write 31 30 29 28 27 26 25 24–––––M

7276264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• MTIMEMARK: Mailbox TimemarkThis field is active in Time Triggered Mode. Transmit operations are all

7286264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ATo prevent concurrent access with the internal CAN core, the application must disable the mailbox bef

7296264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8.14 CAN Message ID RegisterName: CAN_MIDxAccess Type: Read/Write To prevent concurrent access wi

736264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A14. Boot Program14.1 DescriptionThe Boot Program integrates different programs that manage download an

7306264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8.15 CAN Message Family ID RegisterName: CAN_MFIDxAccess Type: Read-only • MFID: Family IDThis fie

7316264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8.16 CAN Message Status RegisterName: CAN_MSRxAccess Type: Read onlyThese register fields are upd

7326264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• MRTR: Mailbox Remote Transmission Request • MABT: Mailbox Message AbortAn interrupt is triggered wh

7336264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• MRDY: Mailbox ReadyAn interrupt is triggered when MRDY is set.0 = Mailbox data registers can not be

7346264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8.17 CAN Message Data Low RegisterName: CAN_MDLxAccess Type: Read/Write• MDL: Message Data Low Va

7356264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8.18 CAN Message Data High RegisterName: CAN_MDHxAccess Type: Read/Write• MDH: Message Data High

7366264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A39.8.19 CAN Message Control RegisterName: CAN_MCRxAccess Type: Write-only • MDLC: Mailbox Data Lengt

7376264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• MACR: Abort Request for Mailbox x It is possible to set MACR field for several mailboxes in the sam

7386264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

7396264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A40. Pulse Width Modulation (PWM) Controller 40.1 DescriptionThe PWM macrocell controls several channe

746264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 14-1. Boot Program Algorithm Flow DiagramTimeout < 1 sCharacter(s) receivedon DBGU ?Run SAM-

7406264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A40.3 I/O Lines DescriptionEach channel outputs one waveform on one external I/O line. 40.4 Product De

7416264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A40.5.1 PWM Clock GeneratorFigure 40-2. Functional View of the Clock Generator Block Diagram Caution:

7426264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AAfter a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode regis-ter are set to

7436264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A or If the waveform is center aligned then the output waveform period depends on the counter source

7446264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AWhen left aligned, the internal channel counter increases up to CPRD and is reset. This endsthe perio

7456264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 40-5. Waveform PropertiesPWM_MCKxCHIDx(PWM_SR)Center AlignedCPRD(PWM_CPRDx)CDTY(PWM_CDTYx)PWM_

7466264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A40.5.3 PWM Controller Operations40.5.3.1 InitializationBefore enabling the output channel, this chann

7476264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 40-6. Synchronized Period or Duty Cycle Update To prevent overwriting the PWM_CUPDx by softwar

7486264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A40.5.3.4 InterruptsDepending on the interrupt mask in the PWM_IMR register, an interrupt is generated

7496264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A40.6.1 PWM Mode RegisterRegister Name: PWM_MRAccess Type: Read/Write• DIVA, DIVB: CLKA, CLKB Divide

756264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A14.3 Device InitializationInitialization follows the steps described below:1. Stack setup for ARM supe

7506264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A40.6.2 PWM Enable RegisterRegister Name: PWM_ENAAccess Type: Write-only• CHIDx: Channel ID0 = No ef

7516264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A40.6.4 PWM Status RegisterRegister Name: PWM_SRAccess Type: Read-only• CHIDx: Channel ID0 = PWM out

7526264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A40.6.5 PWM Interrupt Enable RegisterRegister Name: PWM_IERAccess Type: Write-only • CHIDx: Channel I

7536264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A40.6.7 PWM Interrupt Mask RegisterRegister Name: PWM_IMRAccess Type: Read-only • CHIDx: Channel ID.

7546264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A40.6.9 PWM Channel Mode RegisterRegister Name: PWM_CMRxAccess Type: Read/Write • CPRE: Channel Pre-

7556264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A40.6.10 PWM Channel Duty Cycle RegisterRegister Name: PWM_CDTYxAccess Type: Read/WriteOnly the first

7566264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A40.6.11 PWM Channel Period RegisterRegister Name: PWM_CPRDxAccess Type: Read/WriteOnly the first 16

7576264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A40.6.12 PWM Channel Counter RegisterRegister Name: PWM_CCNTxAccess Type: Read-only• CNT: Channel Co

7586264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

7596264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41. MultiMedia Card Interface (MCI)41.1 DescriptionThe MultiMedia Card Interface (MCI) supports the M

766264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A14.4 DataFlash BootThe DataFlash Boot program searches for a valid application in the SPI DataFlash me

7606264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.2 Block DiagramFigure 41-1. Block Diagram Note: 1. When several MCI (x MCI) are embedded in a prod

7616264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.4 Pin Name List Notes: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain.2. When several MCI

7626264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe MultiMedia Card communication is based on a 7-pin serial bus interface. It has three com-municati

7636264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe SD Memory Card bus includes the signals listed in Table 41-3. Notes: 1. I: input, O: output, PP:

7646264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ACard addressing is implemented using a session address assigned during the initializationphase by the

7656264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe command ALL_SEND_CID and the fields and values for the MCI_CMDR Control Registerare described in

7666264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 41-7. Command/Response Functional Flow Diagram Note: 1. If the command is SEND_OP_COND, the CR

7676264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AConsequent to MMC Specification 3.1, two types of multiple block read (or write) transactionsare defi

7686264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 41-8. Read Functional Flow Diagram Note: 1. It is assumed that this command has been correctly

7696264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.8.3 Write OperationIn write operation, the MCI Mode Register (MCI_MR) is used to define the paddin

776264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 14-5. Structure of the ARM Vector 614.4.2.1 ExampleAn example of valid vectors follows: 00 ea00

7706264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 41-9. Write Functional Flow Diagram Note: 1. It is assumed that this command has been correctl

7716264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe following flowchart shows how to manage a multiple write block transfer with the PDC(see Figure 4

7726264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 41-10. Multiple Write Functional Flow Diagram Note: 1. It is assumed that this command has bee

7736264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.9 SD/SDIO Card OperationsThe MultiMedia Card Interface allows processing of SD Memory (Secure Digi

7746264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.10 MultiMedia Card Interface (MCI) User InterfaceNote: 1. The response register can be read by N a

7756264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.10.1 MCI Control RegisterName: MCI_CRAccess Type: Write-only• MCIEN: Multi-Media Interface Enable

7766264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.10.2 MCI Mode RegisterName: MCI_MRAccess Type: Read/write • CLKDIV: Clock DividerMultimedia Card I

7776264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.10.3 MCI Data Timeout RegisterName: MCI_DTORAccess Type: Read/write • DTOCYC: Data Timeout Cycle

7786264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.10.4 MCI SDCard/SDIO RegisterName: MCI_SDCR Access Type: Read/write • SDCSEL: SDCard/SDIO Slot• SD

7796264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.10.5 MCI Argument RegisterName: MCI_ARGRAccess Type: Read/write • ARG: Command Argument31 30 29 2

786264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 14-6. Serial DataFlash Download14.5 NANDFlash BootThe NANDFlash Boot program searches for a val

7806264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.10.6 MCI Command RegisterName: MCI_CMDRAccess Type: Write-only This register is write-protected w

7816264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A1 = 64-cycle max latency • TRCMD: Transfer Command• TRDIR: Transfer Direction0 = Write1 = Read• TRTYP

7826264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.10.7 MCI Block RegisterName: MCI_BLKRAccess Type: Read/write • BCNT: MMC/SDIO Block Count - SDIO

7836264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.10.8 MCI Response RegisterName: MCI_RSPRAccess Type: Read-only • RSP: ResponseNote: 1. The respon

7846264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.10.9 MCI Receive Data RegisterName: MCI_RDRAccess Type: Read-only • DATA: Data to Read41.10.10 MC

7856264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.10.11 MCI Status RegisterName: MCI_SRAccess Type: Read-only • CMDRDY: Command Ready0 = A command i

7866264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A1 = The Receive Counter Register has reached 0 since the last write in MCI_RCR or MCI_RNCR.• ENDTX: E

7876264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• SDIOIRQA: SDIO Interrupt for Slot A0 = No interrupt detected on SDIO Slot A.1 = A SDIO Interrupt on

7886264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.10.12 MCI Interrupt Enable RegisterName: MCI_IERAccess Type: Write-only • CMDRDY: Command Ready In

7896264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.10.13 MCI Interrupt Disable RegisterName: MCI_IDRAccess Type: Write-only • CMDRDY: Command Ready I

796264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A14.5.1 Supported NANDFlash DevicesAny 8 or 16-bit NANDFlash Devices from 1 Mbit to 16 Gbit density.14.

7906264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A41.10.14 MCI Interrupt Mask RegisterName: MCI_IMRAccess Type: Read-only• CMDRDY: Command Ready Interr

7916264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42. 10/100 Ethernet MAC (EMAC)42.1 DescriptionThe EMAC module implements a 10/100 Ethernet MAC compat

7926264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.3 Functional DescriptionThe MACB has several clock domains:• System bus clock (AHB and APB):

7936264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.3.1.1 FIFOThe FIFO depths are 28 bytes and 28 bytes and area function of the system clock speed, m

7946264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ATo receive frames, the buffer descriptors must be initialized by writing an appropriate address tobit

7956264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Abest to write the pointer register with the least three significant bits set to zero. As receive buff

7966264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Athe control word is read if transmission is to happen. It is written to one when a frame has beentran

7976264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.3.2 Transmit BlockThis block transmits frames in accordance with the Ethernet IEEE 802.3 CSMA/CD p

7986264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.3.3 Pause Frame SupportThe start of an 802.3 pause frame is as follows:The network configuration r

7996264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.3.5 Address Checking BlockThe address checking (or filter) block indicates to the DMA block which

86264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ASCKx USARTx Serial Clock I/OTXDx USARTx Transmit Data I/ORXDx USARTx Receive Data InputRTSx USARTx Requ

806264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A– Output: The byte, halfword or word read in hexadecimal following by ‘>’• Send a file (S): Send a

8006264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe sequence above shows the beginning of an Ethernet frame. Byte order of transmission isfrom top to

8016264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Arx_er asserted during reception are discarded and all others are received. Frames with FCSerrors are

8026264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.3.12 Media Independent InterfaceThe Ethernet MAC is capable of interfacing to both RMII and MII In

8036264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.4 Programming Interface42.4.1 Initialization42.4.1.1 ConfigurationInitialization of the EMAC confi

8046264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.4.1.3 Transmit Buffer ListTransmit data is read from areas of data (the buffers) in system memory

8056264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A8. Write to the transmit start bit in the network control register.42.4.1.7 Receiving FramesWhen a fr

8066264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5 10/100 Ethernet MAC (EMAC) User InterfaceTable 42-6. 10/100 Ethernet MAC (EMAC) Register Mapping

8076264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A0x90 Hash Register Bottom [31:0] Register EMAC_HRB Read/Write 0x0000_00000x94 Hash Register Top [63:3

8086264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.1 Network Control RegisterRegister Name: EMAC_NCRAccess Type: Read/Write• LB: LoopBackAsserts th

8096264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• TSTART: Start transmission Writing one to this bit starts transmission.• THALT: Transmit haltWritin

816264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 14-7. Xmodem Transfer Example 14.6.3 USB Device PortA 48 MHz USB clock is necessary to use the

8106264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.2 Network Configuration RegisterRegister Name: EMAC_NCFGRAccess Type: Read/Write• SPD: SpeedSet

8116264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• CLK: MDC clock dividerSet according to system clock speed. This determines by what number system cl

8126264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.3 Network Status RegisterRegister Name: EMAC_NSRAccess Type: Read-only•MDIOReturns status of the

8136264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.4 Transmit Status RegisterRegister Name: EMAC_TSRAccess Type: Read/WriteThis register, when read

8146264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.5 Receive Buffer Queue Pointer RegisterRegister Name: EMAC_RBQPAccess Type: Read/WriteThis regis

8156264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.6 Transmit Buffer Queue Pointer RegisterRegister Name: EMAC_TBQPAccess Type: Read/WriteThis regi

8166264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.7 Receive Status RegisterRegister Name: EMAC_RSRAccess Type: Read/WriteThis register, when read,

8176264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.8 Interrupt Status RegisterRegister Name: EMAC_ISRAccess Type: Read/Write• MFD: Management Frame

8186264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.9 Interrupt Enable RegisterRegister Name: EMAC_IERAccess Type: Write-only• MFD: Management Frame

8196264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.10 Interrupt Disable RegisterRegister Name: EMAC_IDRAccess Type: Write-only• MFD: Management Fra

826264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe device also handles some class requests defined in the CDC class.Unhandled requests are STALLed.14

8206264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.11 Interrupt Mask RegisterRegister Name: EMAC_IMRAccess Type: Read-only• MFD: Management Frame s

8216264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.12 PHY Maintenance RegisterRegister Name: EMAC_MANAccess Type: Read/Write•DATAFor a write operat

8226264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.13 Pause Time RegisterRegister Name: EMAC_PTRAccess Type: Read/Write• PTIME: Pause TimeStores th

8236264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.14 Hash Register BottomRegister Name: EMAC_HRBAccess Type: Read/Write• ADDR:Bits 31:0 of the has

8246264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.16 Specific Address 1 Bottom RegisterRegister Name: EMAC_SA1BAccess Type: Read/Write• ADDRLeast

8256264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.18 Specific Address 2 Bottom RegisterRegister Name: EMAC_SA2BAccess Type: Read/Write• ADDRLeast

8266264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.20 Specific Address 3 Bottom RegisterRegister Name: EMAC_SA3BAccess Type: Read/Write• ADDRLeast

8276264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.22 Specific Address 4 Bottom RegisterRegister Name: EMAC_SA4BAccess Type: Read/Write• ADDRLeast

8286264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.24 Type ID Checking RegisterRegister Name: EMAC_TIDAccess Type: Read/Write• TID: Type ID checkin

8296264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.25 User Input/Output RegisterRegister Name: EMAC_USRIOAccess Type: Read/Write•RMIIWhen set, this

836264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ABefore performing the jump to the application in internal SRAM, all the PIOs and peripheralsused in th

8306264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.26 EMAC Statistic RegistersThese registers reset to zero on a read and stick at all ones when th

8316264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.26.3 Single Collision Frames RegisterRegister Name: EMAC_SCFAccess Type: Read/Write• SCF: Single

8326264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.26.5 Frames Received OK RegisterRegister Name: EMAC_FROAccess Type: Read/Write• FROK: Frames Rec

8336264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.26.7 Alignment Errors RegisterRegister Name: EMAC_ALEAccess Type: Read/Write• ALE: Alignment Err

8346264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.26.9 Late Collisions RegisterRegister Name: EMAC_LCOLAccess Type: Read/Write• LCOL: Late Collisi

8356264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.26.11 Transmit Underrun Errors RegisterRegister Name: EMAC_TUNDAccess Type: Read/Write• TUND: Tr

8366264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.26.13 Receive Resource Errors RegisterRegister Name: EMAC_RREAccess Type: Read/Write• RRE: Recei

8376264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.26.15 Receive Symbol Errors RegisterRegister Name: EMAC_RSEAccess Type: Read/Write• RSE: Receive

8386264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.26.17 Receive Jabbers RegisterRegister Name: EMAC_RJAAccess Type: Read/Write• RJB: Receive Jabbe

8396264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A42.5.26.19 SQE Test Errors RegisterRegister Name: EMAC_STEAccess Type: Read/Write• SQER: SQE test err

846264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

8406264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

8416264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A43. USB Host Port (UHP)43.1 DescriptionThe USB Host Port (UHP) interfaces the USB with the host appli

8426264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AMemory access errors (abort, misalignment) lead to an “UnrecoverableError” indicated by thecorrespond

8436264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 43-2. USB Host Communication Channels43.4.2 Host Controller DriverFigure 43-3. USB Host Driver

8446264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• USB Bus driver and hub driver: Handles USB commands and enumeration. Offers a hardware independent

8456264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A43.5 Typical ConnectionFigure 43-4. Board Schematic to Interface UHP Device ControllerA termination s

8466264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

8476264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44. USB High Speed Device Port (UDPHS)44.1 DescriptionThe USB High Speed Device Port (UDPHS) is compl

8486264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.2 Block DiagramFigure 44-1. Block Diagram: 32 bitsSystem ClockDomainUSB ClockDomainctrlstatusRd/Wr

8496264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.3 Typical ConnectionFigure 44-2. Board Schematic Note: The values shown on the 22 kΩ and 15 kΩ res

856264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A15. Reset Controller (RSTC)15.1 DescriptionThe Reset Controller (RSTC), based on power-on reset cells,

8506264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A 44.4.3 USB Transfer Event DefinitionsA transfer is composed of one or several transactions;Notes: 1.

8516264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 44-3. Control Read and Write SequencesA status IN or OUT transaction is identical to a data IN

8526264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A+ NB_BANK_EPT1 x SIZE_EPT1+ NB_BANK_EPT2 x SIZE_EPT2+ NB_BANK_EPT3 x SIZE_EPT3+ NB_BANK_EPT4 x SIZE_E

8536264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A– EPT_ENABL: Enable endpoint.Configuration examples of Bulk OUT endpoint type follow below.•With DMA–

8546264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.4.6 Transfer With DMAUSB packets of any length may be transferred when required by the UDPHS Devic

8556264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.4.7 Transfer Without DMAImportant. If the DMA is not to be used, it is neccessary that it be disab

8566264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThus, firmware must detect RX_SETUP polling UDPHS_EPTSTAx or catching an interrupt, readthe setup pac

8576264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AA simple algorithm can be used by the application to send packets regardless of the number ofbanks as

8586264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A– Size of buffer to send: size of the buffer to be sent to the host.– END_B_EN: The endpoint can vali

8596264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 44-7. Data IN Transfer for Endpoint with One Bank Figure 44-8. Data IN Transfer for Endpoint w

866264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe startup counter waits for the complete crystal oscillator startup. The wait delay is given bythe c

8606264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 44-9. Data IN Followed By Status OUT Transfer at the End of a Control TransferNote: A NAK hand

8616264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 44-11. Autovalid with DMANote: In the illustration above Autovalid validates a bank as full, a

8626264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250Athe required number of packets per microframe, otherwise, the host will notice a sequencingproblem.A

8636264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• ERR_FL_ISO + ERR_FLUSH + ERR_TRANS: The first token IN has been treated, the data for the second To

8646264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A– END_BUFFIT: Generate an interrupt when BUFF_COUNT in the UDPHS_DMASTATUSx register reaches 0.– END_

8656264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 44-13. Data OUT Transfer for an Endpoint with Two Banks44.4.8.13 High Bandwidth Isochronous En

8666264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AExample: • If NB_TRANS = 3, the sequence should be either–MData0 – MData0/Data1 – MData0/Data1/Data2•

8676264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.4.8.15 STALLSTALL is returned by a function in response to an IN token or after the data phase of

8686264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.4.9 Speed IdentificationThe high speed reset is managed by the hardware.At the connection, the hos

8696264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 44-17. UDPHS Interrupt Control InterfaceDET_SUSPDMICRO_SOFIEN_SOFENDRESETWAKE_UPENDOFRSMUPSTR_

876264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AAs the field is within RSTC_MR, which is backed-up, this field can be used to shape the systempower-up

8706264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.4.12 Power Modes44.4.12.1 Controlling Device States A USB device has several possible states. Refe

8716264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.4.12.2 Not Powered StateSelf powered devices can detect 5V VBUS using a PIO. When the device is no

8726264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.4.12.7 Entering Suspend State (Bus Activity)When a Suspend (no bus activity on the USB bus) is det

8736264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.4.13 Test ModeA device must support the TEST_MODE feature when in the Default, Address or Configur

8746264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5 USB High Speed Device Port (UDPHS) User InterfaceNotes: 1. The reset value for UDPHS_EPTCTL0 is

8756264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.1 UDPHS Control RegisterName: UDPHS_CTRLAccess Type: Read/Write• DEV_ADDR: UDPHS AddressRead:Thi

8766264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A0 = UDPHS is attached.1 = UDPHS is detached, UTMI transceiver is suspended.Write:0 = pull up the DP l

8776264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.2 UDPHS Frame Number RegisterName: UDPHS_FNUMAccess Type: Read • MICRO_FRAME_NUM: Microframe Num

8786264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.3 UDPHS Interrupt Enable RegisterName: UDPHS_IENAccess Type: Read/Write • DET_SUSPD: Suspend Int

8796264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• ENDRESET: End Of Reset Interrupt EnableRead:0 = End Of Reset Interrupt is disabled.1 = End Of Reset

886264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 15-4. General Reset StateSLCKperiph_nresetproc_nresetBackup SupplyPOR outputNRST(nrst_out)EXTER

8806264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A1 = enable the interrupts for this endpoint.• DMA_INT_x: DMA Channel x Interrupt EnableRead:0 = the i

8816264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.4 UDPHS Interrupt Status RegisterName: UDPHS_INTSTAAccess Type: Read-only• SPEED: Speed Status0

8826264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• WAKE_UP: Wake Up CPU Interrupt0 = cleared by setting the WAKE_UP bit in UDPHS_CLRINT.1 = set by har

8836264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.5 UDPHS Clear Interrupt RegisterName: UDPHS_CLRINTAccess Type: Write only• DET_SUSPD: Suspend In

8846264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.6 UDPHS Endpoints Reset RegisterName: UDPHS_EPTRSTAccess Type: Write only• EPT_x: Endpoint x Res

8856264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.7 UDPHS Test RegisterName: UDPHS_TSTAccess Type: Read/Write • SPEED_CFG: Speed ConfigurationRead

8866264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A0 = no effect.1 = set to force the OpMode signal (UTMI interface) to “10”, to disable the bit-stuffin

8876264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.8 UDPHS Endpoint Configuration RegisterName: UDPHS_EPTCFGx [x=0..7]Access Type: Read/Write •

8886264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A:Endpoint Type• BK_NUMBER: Number of BanksRead and write:Set this field according to the endpoint’s n

8896264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.9 UDPHS Endpoint Control Enable RegisterName: UDPHS_EPTCTLENBx [x=0..7]Access Type: Write-onl

896264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A15.3.4.2 Wake-up ResetThe Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR

8906264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A1 = enable Overflow Error Interrupt.• RX_BK_RDY: Received OUT Data Interrupt Enable0 = no effect.1 =

8916264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.10 UDPHS Endpoint Control Disable RegisterName: UDPHS_EPTCTLDISx [x=0..7]Access Type: Write-o

8926264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A1 = disable Overflow Error Interrupt.• RX_BK_RDY: Received OUT Data Interrupt Disable0 = no effect.1

8936264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.11 UDPHS Endpoint Control RegisterName: UDPHS_EPTCTLx [x=0..7]Access Type: Read-only • EPT_EN

8946264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThis may be used, for example, to identify or prevent an erroneous packet to be transferred into a bu

8956264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A0 = Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.1 = Stall Sent /ISO CRC

8966264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.12 UDPHS Endpoint Set Status RegisterName: UDPHS_EPTSETSTAx [x=0..7]Access Type: Write-only

8976264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.13 UDPHS Endpoint Clear Status RegisterName: UDPHS_EPTCLRSTAx [x=0..7]Access Type: Write-only

8986264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• NAK_OUT: NAKOUT Clear0 = no effect.1 = clear the NAK_OUT flag of UDPHS_EPTSTAx.

8996264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.14 UDPHS Endpoint Status RegisterName: UDPHS_EPTSTAx [x=0..7]Access Type: Read-only • FRCEST

96264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ALCD Controller - LCDCLCDD0 - LCDD23 LCD Data Bus InputLCDVSYNC LCD Vertical Synchronization OutputLCDHS

906264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A15.3.4.3 User ResetThe User Reset is entered when a low level is detected on the NRST pin and the bit

9006264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• ERR_OVFLW: Overflow ErrorThis bit is set by hardware when a new too-long packet is received. Exampl

9016264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AIf one toggle sequencing problem occurs among the n-transactions (n = 1, 2 or 3) inside a microframe,

9026264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThis bit is set when flushing unsent banks at the end of a microframe.This bit is reset by UDPHS_EPTR

9036264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThis field is also updated at TX_PK_RDY flag set with the next bank.This field is reset by EPT_x of U

9046264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.15 UDPHS DMA Channel Transfer DescriptorThe DMA channel transfer descriptor is loaded from the m

9056264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.16 UDPHS DMA Next Descriptor Address RegisterName: UDPHS_DMANXTDSCx [x = 1..6]Access Type: R

9066264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.17 UDPHS DMA Channel Address RegisterName: UDPHS_DMAADDRESSx [x = 1..6]Access Type: Read/Writ

9076264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.18 UDPHS DMA Channel Control RegisterName: UDPHS_DMACONTROLx [x = 1..6]Access Type: Read/Writ

9086264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• END_TR_EN: End of Transfer Enable (Control)Used for OUT transfers only.0 = USB end of transfer is i

9096264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A44.5.19 UDPHS DMA Channel Status RegisterName: UDPHS_DMASTATUSx [x = 1..6]Access Type: Read/Write•

916264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A15.3.4.4 Software ResetThe Reset Controller offers several commands used to assert the different reset

9106264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A0 = cleared automatically when read by software.1 = set by hardware when a descriptor has been loaded

9116264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45. Image Sensor Interface (ISI)45.1 OverviewThe Image Sensor Interface (ISI) connects a CMOS-type im

9126264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.2 Block DiagramFigure 45-2. Image Sensor Interface Block Diagram45.3 Functional DescriptionThe Ima

9136264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.3.1 Data TimingThe two data timings using horizontal and vertical synchronization and EAV/SAV sequ

9146264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.3.2 Data OrderingThe RGB color space format is required for viewing images on a display screen pre

9156264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AThe RGB 5:6:5 input format is processed to be displayed as RGB 5:5:5 format, compliant withthe 16-bit

9166264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.3.4 Preview Path45.3.4.1 Scaling, Decimation (Subsampling)This module resizes captured 8-bit color

9176264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 45-5. Resize Examples 45.3.4.2 Color Space ConversionThis module converts YCrCb or YUV pixels

9186264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.3.4.3 Memory InterfacePreview datapath contains a data formatter that converts 8:8:8 pixel to RGB

9196264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 45-6. Three Frame Buffers Application and Memory Mapping 45.3.5 Codec Path45.3.5.1 Color Space

926264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 15-7. Software ResetSLCKperiph_nresetif PERRST=1proc_nresetif PROCRST=1Write RSTC_CRNRST(nrst_o

9206264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.3.5.2 Memory InterfaceDedicated FIFO are used to support packed memory mapping. YCrCb pixel compon

9216264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.4 Image Sensor Interface (ISI) User InterfaceNote: Several parts of the ISI controller use the pix

9226264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.4.1 ISI Control 1 RegisterRegister Name: ISI_CR1Access Type: Read/WriteReset Value: 0x00000002• IS

9236264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A1: CRC correction is performed. if the correction is not possible, the current frame is discarded and

9246264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.4.2 ISI Control 2 RegisterRegister Name: ISI_CR2Access Type: Read/WriteReset Value: 0x0 • IM_VSIZE

9256264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• YCC_SWAP: Defines the YCC image data• RGB_CFG: Defines RGB pattern when RGB_MODE is set to 1If RGB_

9266264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.4.3 ISI Status RegisterRegister Name: ISI_SRAccess Type: ReadReset Value: 0x0• SOF: Start of frame

9276264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A0: No overflow1: An overrun condition has occurred in input FIFO on the preview path. The overrun hap

9286264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.4.4 Interrupt Enable RegisterRegister Name: ISI_IERAccess Type: Read/WriteReset Value: 0x0• SOF: S

9296264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.4.5 ISI Interrupt Disable RegisterRegister Name: ISI_IDRAccess Type: Read/WriteReset Value: 0x0• S

936264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A15.3.4.5 Watchdog ResetThe Watchdog Reset is entered when a watchdog fault occurs. This state lasts Y

9306264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.4.6 ISI Interrupt Mask RegisterRegister Name: ISI_IMRAccess Type: Read/WriteReset Value: 0x0• SOF:

9316264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A0: The codec FIFO empty interrupt is disabled.1: The codec FIFO empty interrupt is enabled.•FR_OVR: F

9326264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.4.7 ISI Preview RegisterRegister Name: ISI_PSIZEAccess Type: Read/WriteReset Value: 0x0 • PREV_VSI

9336264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.4.8 ISI Preview Decimation Factor RegisterRegister Name: ISI_PDECFAccess Type: Read/WriteReset Val

9346264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.4.9 ISI Preview Primary FBD RegisterRegister Name: ISI_PPFBDAccess Type: Read/WriteReset Value: 0x

9356264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.4.10 ISI Codec DMA Base Address RegisterRegister Name: ISI_CDBAAccess Type: Read/WriteReset Value:

9366264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.4.11 ISI Color Space Conversion YCrCb to RGB Set 0 RegisterRegister Name: ISI_Y2R_SET0Access Type:

9376264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.4.12 ISI Color Space Conversion YCrCb to RGB Set 1 RegisterRegister Name: ISI_Y2R_SET1Access Type:

9386264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.4.13 ISI Color Space Conversion RGB to YCrCb Set 0 RegisterRegister Name: ISI_R2Y_SET0Access Type:

9396264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.4.14 ISI Color Space Conversion RGB to YCrCb Set 1 RegisterRegister Name: ISI_R2Y_SET1Access Type:

946264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• When in User Reset: – A watchdog event is impossible because the Watchdog Timer is being reset by th

9406264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A45.4.15 ISI Color Space Conversion RGB to YCrCb Set 2 RegisterRegister Name: ISI_R2Y_SET2Access Type:

9416264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A46. Analog-to-Digital Converter (ADC)46.1 DescriptionThe ADC is based on a Successive Approximation R

9426264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A46.3 Signal Description 46.4 Product Dependencies46.4.1 Power ManagementThe ADC is automatically cloc

9436264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A46.5 Functional Description46.5.1 Analog-to-digital ConversionThe ADC uses the ADC Clock to perform c

9446264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A46.5.4 Conversion ResultsWhen a conversion is completed, the resulting 10-bit digital value is stored

9456264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AIf the ADC_CDR is not read before further incoming data is converted, the corresponding Over-run Erro

9466264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A46.5.5 Conversion TriggersConversions of the active analog channels are started with a software or a

9476264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A46.5.7 ADC TimingsEach ADC has its own minimal Startup Time that is programmed through the field STAR

9486264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A46.6 Analog-to-digital Converter (ADC) User InterfaceTable 46-2. ADC Register MappingOffset Register

9496264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A46.6.1 ADC Control Register Register Name: ADC_CRAccess Type: Write-only • SWRST: Software Reset0 = N

956264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A15.4 Reset Controller (RSTC) User InterfaceNote: 1. The reset value of RSTC_SR either reports a Genera

9506264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A46.6.2 ADC Mode RegisterRegister Name: ADC_MRAccess Type: Read/Write• TRGEN: Trigger Enable • TRGSEL

9516264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A• PRESCAL: Prescaler Rate Selection ADCClock = MCK / ( (PRESCAL+1) * 2 )• STARTUP: Start Up TimeStart

9526264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A46.6.3 ADC Channel Enable Register Register Name: ADC_CHERAccess Type: Write-only • CHx: Channel x E

9536264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A46.6.5 ADC Channel Status Register Register Name: ADC_CHSRAccess Type: Read-only • CHx: Channel x Sta

9546264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A46.6.6 ADC Status Register Register Name: ADC_SRAccess Type: Read-only • EOCx: End of Conversion x0

9556264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A46.6.7 ADC Last Converted Data RegisterRegister Name: ADC_LCDRAccess Type: Read-only • LDATA: Last Da

9566264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A46.6.9 ADC Interrupt Disable Register Register Name: ADC_IDRAccess Type: Write-only • EOCx: End of C

9576264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A46.6.10 ADC Interrupt Mask Register Register Name: ADC_IMRAccess Type: Read-only • EOCx: End of Conv

9586264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A46.6.11 ADC Channel Data RegisterRegister Name: ADC_CDRxAccess Type: Read-only• DATA: Converted DataT

9596264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47. AT91CAP9 Electrical Characteristics47.1 Absolute Maximum Ratings47.2 DC CharacteristicsThe follow

966264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A15.4.1 Reset Controller Control RegisterRegister Name: RSTC_CRAccess Type: Write-only• PROCRST: Proces

9606264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.3 Power ConsumptionThis section contains:• The typical power consumption of PLLs, Slow Clock and M

9616264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ATable 47-3. Power Consumption for different Modes(1)Mode Conditions Consumption UnitActiveARM Core cl

9626264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.4 32 kHz Crystal Oscillator CharacteristicsThe following characteristics are applicable to the ope

9636264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.5 12 MHz Main Oscillator CharacteristicsThe following characteristics are applicable to the operat

9646264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ANote: These characteristics apply only when Main Oscillator is in Bypass Mode (i.e., when MOSCEN = 0

9656264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.8 USB HS CharacteristicsThe following characteristics are applicable to the operating temperature

9666264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.8.3 Dynamic Power ConsumptionNote: 1. Including 1mA due to Pull-up/Pull-down current consumption.T

9676264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.9 ADC Notes: 1. Corresponds to 13 clock cycles at 5 MHz: 3 clock cycles for track and hold acquisi

9686264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.10 Timings47.10.1 Corner Definition Timings in MAX corner always result from the extraction and co

9696264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.10.4 SMC Timings47.10.4.1 CapacitanceTimings are given assuming a capacitance load on data, contro

976264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A15.4.2 Reset Controller Status RegisterRegister Name: RSTC_SRAccess Type: Read-only• URSTS: User Reset

9706264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.10.4.3 Write Timings Notes: 1. hold length = total cycle duration - setup duration - pulse duratio

9716264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 47-3. SMC Timings - NCS Controlled Read and WriteSMC25NWE low before NCS high(ncs wr setup - n

9726264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 47-4. SMC Timings - NRD Controlled Read and NWE Controlled Write NRDNCSD0 - D31NWEA0/A1/NBS[3:

9736264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.10.5 SDRAMC TimingsThe SDRAM Controller satisfies the timings of standard SDRAM modules (SDRAM or

9746264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 47-5. SDRAMC TimingsThe timings of the SDRAM controller support the use of PC100, PC133 (3.3V

9756264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ANotes: 1. Control is the set of following timings : A0-A9, A11-A13, SDCKE, SDCS, RAS, CAS, SDA10, BAx

9766264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.10.6 DDR SDRAMC TimingsThe DDR SDRAM controller satisfies the timings of standard Mobile SDRAM, ti

9776264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 47-6. DDRSDRC Timings The timings of the DDR SDRAM controller support the use of LPDDR200 Doub

9786264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.10.7 SPIFigure 47-7. SPI Master Mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) Figure 47-8. SPI

9796264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 47-10. SPI Slave Mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) Notes: 1. Cload is 8pF for M

986264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A15.4.3 Reset Controller Mode RegisterRegister Name: RSTC_MRAccess Type: Read/Write• URSTEN: User Reset

9806264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.10.8 ISI TimingsFigure 47-11. ISI Timing Diagram Table 47-37. ISI Timings with Peripheral Supply 3

9816264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.10.9 MCI TimingsThe PDC interface block controls all data routing between the external data bus, i

9826264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AMCI2Input hold time TBD nsMCI3Input setup time TBD nsMCI4Output change after CLK rising TBD nsMCI5Out

9836264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.10.10 UDP TimingsFigure 47-13. USB Data Signal Rise and Fall Times orFigure 47-14. USB Data Signal

9846264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.10.11 EMAC TimingsThe Ethernet controller satisfies the timings of standard given in Table 47-45 a

9856264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250AFigure 47-15. EMAC MII Mode EMDCEMDIOECOLECRSETXCKETXERETXENETX[3:0]ERXCKERX[3:0]ERXERERXDVEMAC3EMAC1

9866264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.10.11.2 RMII Mode Figure 47-16. EMAC RMII Timings Table 47-47. RMII ModeSymbol Parameter Min (ns)

9876264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A47.10.12 AC97 TimingsFigure 47-17. Data Setup and Hold Table 47-48. AC97 Data Setup and HoldSymbol Pa

9886264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A48. AT91CAP9 Mechanical Characteristics48.1 Thermal Considerations48.1.1 Thermal DataTable 48-1 summa

9896264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A48.2 Package DrawingFigure 48-1. 400-ball LFBGA Package DrawingThis package respects the recommendati

996264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A16. Real-time Timer (RTT)16.1 OverviewThe Real-time Timer is built around a 32-bit counter and used to

9906264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A48.3 Soldering ProfileTable 48-6 gives the recommended soldering profile from J-STD-020C.Note: It is

9916264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A49. AT91CAP9 Ordering Information Table 49-1. AT91CAP9 Ordering InformationOrdering Code Package Pack

9926264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

9936264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A50. AT91CAP9 Errata50.1 MarkingAll devices are marked with the Atmel logo and the ordering code.Addit

9946264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

9956264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A51. Revision HistoryTable 51-1.Revision CommentsChange Request Ref.6264A First issue.

9966264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A

i6264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250ATable of ContentsFeatures ...

ii6264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A9.2 Reset Controller ......

iii6264A–CAP–21-May-07AT91CAP9S500A/AT91CAP9S250A13.5 Functional Description ..................