Rainbow-electronics ATmega128L Manual do Utilizador descarregar pdf (Página 51)

ATmega128(L)

2467B–09/01

Figure 27. Watchdog Timer

Watchdog Timer Control

• Bits 7..5 - Res: Reserved Bits

These bits are reserved bits in the ATmega128 and will always read as zero.

• Bit 4 - WDCE: Watchdog Change Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the watchdog

will not be disabled. Once written to one, hardware will clear this bit after four clock

cycles. Refer to the description of the WDE bit for a watchdog disable procedure. In

Safety Level 1 and 2, this bit must also be set when changing the prescaler bits.

See

“Timed Sequences for Changing the Configuration of the Watch Dog Timer” on page 53.

• Bit 3 - WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is

written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared

if the WDCE bit has logic level one. To disable an enabled watchdog timer, the following

procedure must be followed:

Table 21. WDT Configuration as a Function of the Fuse Settings of M103C and

WDTON.

M103C WDTON

Safety

Level

WDT Initial

State

How to Disable

the WDT

How to

Change

Time-out

Unprogrammed Unprogrammed 1 Disabled Timed

sequence

Timed

sequence

Unprogrammed Programmed 2 Enabled Always enabled Timed

sequence

Programmed Unprogrammed 0 Disabled Timed

sequence

restriction

Programmed Programmed 2 Enabled Always enabled Timed

sequence

WATCHDOG

OSCILLATOR

Bit 76543210

–––WDCE WDE WDP2 WDP1 WDP0 WDTCR

Read/Write R R R R/W R/W R/W R/W R/W

Initial value00000000

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 330 331

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