Rainbow-electronics ATmega128L Manual do Utilizador Página 163
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163
ATmega128(L)
2467B–09/01
SPIF bit is cleared by first reading the SPI status register with SPIF set, then accessing
the SPI Data Register (SPDR).
• Bit 6 - WCOL: Write COLlision flag
The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with
WCOL set, and then accessing the SPI Data Register.
• Bit 5..1 - Res: Reserved Bits
These bits are reserved bits in the ATmega128 and will always read as zero.
• Bit 0 - SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when
the SPI is in master mode (see
Table 72). This means that the minimum SCK period will
be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaran-
teed to work at f
osc
/ 4 or lower.
The SPI interface on the ATmega128 is also used for program memory and EEPROM
downloading or uploading. See page 292 for serial programming and verification.
SPI Data Register – SPDR
The SPI Data Register is a read/write register used for data transfer between the regis-
ter file and the SPI Shift register. Writing to the register initiates data transmission.
Reading the register causes the Shift Register Receive buffer to be read.
Data Modes There are four combinations of SCK phase and polarity with respect to serial data,
which are determined by control bits CPHA and CPOL. The SPI data transfer formats
are shown in
Figure 76 and Figure 77. Data bits are shifted out and latched in on oppo-
site edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is
clearly seen by summarizing
Table 70 and Table 71, as done below:
Bit 76543210
MSB LSB SPDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial valueXXXXXXXXUndefined
Table 73. CPOL Functionality
Leading edge Trailing edge SPI mode
CPOL = 0, CPHA = 0 Sample (Rising) Setup (Falling) 0
CPOL = 0, CPHA = 1 Setup (Rising) Sample (Falling) 1
CPOL = 1, CPHA = 0 Sample (Falling) Setup (Rising) 2
CPOL = 1, CPHA = 1 Setup (Falling) Sample (Rising) 3
- Features 1
- ATmega128(L) 10
- Table 55 on 95
- OCnPCPWM 96
- MAX - 1 MAX BOTTOM BOTTOM + 1 97
- 8-bit Timer/Counter 98
- Register Description 98
- “Access 107
- DATABUS (8-bit) 112
- (Toggle) 118
- OCnxPFCPWM 125
- OCRnx Value 126
- 2467B–09/01 150
- Oscillator 251
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