
79
AT90S/LS4433
1042G–AVR–09/02
Port C Schematics Note that all port pins are synchronized. The synchronization latch is, however, not
shown in the figure.
Figure 56. Port C Schematic Diagrams (Pins PC0 - PC5)
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PCn
ADCn
TO ADC MUX
WP:
WD:
RL:
RP:
RD:
n:
WRITE PORTC
WRITE DDRC
READ PORTC LATCH
READ PORTC PIN
READ DDRC
0 - 5
DDCn
PORTCn
RL
RP
PWRDN
PWRDN:
POWER DOWN MODE
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