
76
AT90S/LS4433
1042G–AVR–09/02
Figure 53. Port B Schematic Diagram (Pin PB3)
Figure 54. Port B Schematic Diagram (Pin PB4)
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PB3
R
R
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
DDB3
PORTB3
SPE
MSTR
SPI MASTER
OUT
SPI SLAVE
IN
RL
RP
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PB4
R
R
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
DDB4
PORTB4
SPE
MSTR
SPI SLAVE
OUT
SPI MASTER
IN
RL
RP
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