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NUC120 Series DATA SHEET

5 FUNCTIONAL DESCRIPTION

5.1 ARM

Cortex™-M0 core

The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA

AHB-Lite interface and includes an NVIC component. It also has optional hardware debug

functionality. The processor can execute Thumb code and is compatible with other Cortex-M profile

processor.

Figure 5-1 shows the functional blocks of processor.

Publication Release Date: May 31, 2010

- 22 - Revision V1.02

Cortex-M0

Processor

core

Nested

Vectored

Interrupt

Controller

(NVIC)

Breakpoint

and

Watchpoint

unit

Debugger

interface

Bus matrix

Debug

Access Port

(DAP)

DebugCortex-M0 processor

Cortex-M0 components

Interrupts

Wakeup

Interrupt

Controller

(WIC)

Serial Wire or

JTAG debug port

AHB-Lite interface

Figure 5-1 Functional Block Diagram

The implemented device provides:

• A low gate count processor that features:

– The ARMv6-M Thumb® instruction set.

– Thumb-2 technology.

– ARMv6-M compliant 24-bit SysTick timer.

– A 32-bit hardware multiplier.

– The system interface supports little-endian data accesses.

– The ability to have deterministic, fixed-latency, interrupt handling.

– Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to facilitate

rapid interrupt handling.

– C Application Binary Interface compliant exception model.

This is the ARMv6-M, C Application Binary Interface(C-ABI) compliant exception model that

enables the use of pure C functions as interrupt handlers.

– Low power sleep-mode entry using Wait For Interrupt(WFI), Wait For Even(WFE) instructions,

or the return from interrupt sleep-on-exit feature.

• NVIC that features:

– 32 external interrupt inputs, each with four levels of priority.

– Dedicated non-Maskable Interrupt (NMI) input.

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