Rainbow-electronics MAX5937 Manual do Utilizador descarregar pdf (Página 9)

MAX5936/MAX5937

-48V Hot-Swap Controllers with V

Step Immunity and No R

SENSE

_______________________________________________________________________________________ 9

In a normal power-up GATE cycle, the voltage at V

OUT

(referenced to V

) ramps to below 74% of the circuit-

breaker threshold voltage, V

. At this time, the remaining

GATE voltage is rapidly pulled up to full enhancement.

PGOOD is asserted 1.26ms after GATE is fully enhanced

(see Figure 4). If the voltage at V

OUT

remains above 74%

of the V

(when GATE reaches 90% of full enhance-

ment), then a power-up to fault management fault has

occurred (see Figure 5). GATE is rapidly pulled to V

turning off the power MOSFET and disconnecting the

load. PGOOD remains deasserted and the MAX5936/

MAX5937 enter the fault management mode.

When the power MOSFET is fully enhanced, the

MAX5936/MAX5937 monitor the drain voltage (V

OUT

) for

circuit-breaker and short-circuit faults. The MAX5936/

MAX5937 make use of the power MOSFET’s R

DS(ON)

the current-sense resistance to detect excessive current

through the load. The short-circuit threshold voltage,

, is twice V

= 2 x V

) and is available in

100mV, 200mV, and 400mV thresholds. V

and V

are temperature-compensated (increasing with tempera-

ture) to track the normalized temperature coefficient of

DS(ON)

for typical power MOSFETs.

When the load current is increased during full enhance-

ment, this causes V

OUT

to exceed V

but remains less

than V

, and starts the 1.2ms circuit-breaker glitch

rejection timer. At the end of the glitch rejection period,

if V

OUT

still exceeds V

, the GATE is immediately

pulled to V

(330ns), PGOOD (PGOOD) is deasserted,

and the part enters fault management. Alternatively,

during full enhancement when V

OUT

exceeds V

there is no glitch rejection timer. GATE is immediately

pulled to V

, PGOOD is deasserted, and the part

enters fault management.

Figure 3. Load Probe Test During Initial Power-Up

40ms/div

20V/div

OUT

20V/div

ALL VOLTAGES

REFERENCED TO GND

Figure 2. GATE Voltage Clamp During Power-Up

20V/div

GATE

1V/div

4ms/div

= 100µF

Figure 4. MAX5936 Normal Condition

50V/div

PGOOD

50V/div

40ms/div

GATE

10V/div

OUT

50V/div

2A/div

Figure 5. MAX5936 Startup in Fault Condition

50V/div

PGOOD

50V/div

40ms/div

GATE

10V/div

OUT

50V/div

2A/div

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 22 23

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