MAX148/MAX149
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
_______________________________________________________________________________________ 7
______________________________________________________________Pin Description
Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to V
DD
.REFADJ12
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX148/MAX149 begin the
A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses
high for one clock period before the MSB decision. High impedance when CS is high (external clock
mode).
SSTRB16
Serial-Data Input. Data is clocked in at SCLK’s rising edge.DIN17
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
CS
18
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
SCLK19
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode (MAX149 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to V
DD
.
VREF11
Analog GroundAGND13
Digital GroundDGND14
Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
DOUT15
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX148/MAX149 down; otherwise, they are
fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation mode.
Letting SHDN float puts the reference-buffer amplifier in external compensation mode.
SHDN
10
Ground reference for analog inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.
COM9
PIN
Sampling Analog InputsCH0–CH71–8
FUNCTIONNAME
Positive Supply VoltageV
DD
20
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