MAX1422
12-Bit, 20Msps, +3.3V, Low-Power ADC with
Internal Reference
4 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CLK, CLK ±330
PD -20 20
Input Current
OE -20 20
µA
Input Capacitance 10 pF
DIGITAL OUTPUTS (D0–D11)
Output Logic High V
OH
I
OH
= 200µA
V
D V DD
- 0.5
V
DVDD
V
Output Logic Low V
OL
I
OL
= -200µA00.5V
Three-State Leakage -10 10 µA
Three-State Capacitance 2pF
POWER REQUIREMENTS
Analog Supply Voltage V
AVDD
3.138 3.3 3.465 V
Digital Supply Voltage V
DVDD
2.7 3.3 3.63 V
Analog Supply Current I
AVDD
39 46 mA
Analog Supply Current with
Internal Reference in Shutdown
REFIN
= AGND 37 44 mA
Analog Shutdown Current PD = DV
DD
20 µA
Digital Supply Current I
DVDD
3mA
Digital Shutdown Current PD = DV
DD
20 µA
Power Dissipation P
DISS
Analog power dissipation 137 152 mW
Power-Supply Rejection Ratio PSRR (Note 9) ±1 mV/V
TIMING CHARACTERISTICS
Clock Frequency f
CLK
Figure 5 0.1 20 MHz
Clock High t
CH
Figure 5, clock period 50ns 25 ns
Clock Low t
CL
Figure 5, clock period 50ns 25 ns
Pipeline Delay (Latency) Figure 5 7
f
CLK
Cycles
Aperture Delay t
AD
Figure 9 2 ns
Aperture Jitter t
AJ
Figure 9 2 ps
Data Output Delay t
OD
Figure 5 5 10 14 ns
Bus Enable Time t
BE
Figure 4 5 ns
Bus Disable Time t
BD
Figure 4 5 ns
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
DVDD
= +3.3V, AGND = DGND = 0, V
IN
= ±1.024V, differential input voltage at -0.5dB FS, +2.048V internal reference, f
CLK
=
20MHz (50% duty cycle), digital output load C
L
≈ 10pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
Note 1: Internal reference, REFIN bypassed to AGND with a combination of 0.22µF in parallel with 1nF capacitor.
Note 2: External +2.048V reference applied to REFIN.
Note 3: Internal reference disabled. V
REFIN
= 0, V
REFP
= +2.162V, V
CML
= +1.65V, and V
REFN
= +1.138V.
Note 4: IMD is measured with respect to either of the fundamental tones.
Note 5: Specifies the common-mode range of the differential input signal supplied to the MAX1422.
Note 6: V
DIFF
= V
REFP
- V
REFN.
Note 7: Input bandwidth is measured at a 3dB level.
Note 8: V
REFIN
is internally biased to +2.048V through a 10kΩ resistor.
Note 9: Measured as the ratio of the change in mid-scale offset voltage for a ±5% change in V
AVDD
, using the internal reference.
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