General DescriptionThe MAX1422 +3.3V, 12-bit analog-to-digital converter(ADC) features a fully-differential input, pipelined, 12-stage ADC architectur
MAX1422these nodes become high impedance and can be drivenby external reference sources, as shown in Figure 3.Clock Inputs (CLK, CLK)The MAX1422’s CLK
log portion of the MAX1421, thereby degrading itsdynamic performance. The use of digital buffers (e.g.74LVCH16244) on the digital outputs of the ADCs
MAX1422Single-Ended, AC-Coupled Input SignalFigure 9 shows an AC-coupled, single-ended applica-tion, using a MAX4108 op amp. This configuration pro-vi
Aperture DelayAperture delay (tAD) is the time defined between thefalling edge of the sampling clock and the instant whenan actual sample is taken (Fi
MAX1422Total Harmonic Distortion (THD)THD is typically the ratio of the RMS sum of the first fourharmonics of the input signal to the fundamental itse
MAX142212-Bit, 20Msps, +3.3V, Low-Power ADC withInternal ReferencePackage Information32L/48L,TQFP.EPSMaxim cannot assume responsibility for use of any
MAX142212-Bit, 20Msps, +3.3V, Low-Power ADC withInternal Reference2 __________________________________________________________________________________
MAX142212-Bit, 20Msps, +3.3V, Low-Power ADC withInternal Reference____________________________________________________________________________________
MAX142212-Bit, 20Msps, +3.3V, Low-Power ADC withInternal Reference4 __________________________________________________________________________________
MAX142212-Bit, 20Msps, +3.3V, Low-Power ADC withInternal Reference____________________________________________________________________________________
MAX142212-Bit, 20Msps, +3.3V, Low-Power ADC withInternal Reference6 __________________________________________________________________________________
MAX142212-Bit, 20Msps, +3.3V, Low-Power ADC withInternal Reference____________________________________________________________________________________
MAX1422Detailed DescriptionThe MAX1422 uses a 12-stage, fully-differential,pipelined architecture (Figure 1), that allows for high-speed conversion wh
Input Track-and-Hold Transconductance CircuitFigure 2 displays a simplified functional diagram of theinput track-and-hold (T/H) circuit in both track-
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