Rainbow-electronics MAX1181 Manual do Utilizador descarregar pdf (Página 5)

MAX1181

Dual 10-Bit, 80Msps, +3V, Low-Power ADC with

Internal Reference and Parallel Outputs

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FFT PLOT CHA (8192-POINT RECORD,

DIFFERENTIAL INPUT)

MAX1181 toc01

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

INA

= 6.0449MHz

INB

= 7.5099MHz

CLK

= 80.000568MHz

AINA = -0.46dB FS

CHA

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FFT PLOT CHB (8192-POINT RECORD,

DIFFERENTIAL INPUT)

MAX1181 toc02

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

INA

= 6.0449MHz

INB

= 7.5099MHz

CLK

= 80.000568MHz

AINB = -0.52dB FS

CHB

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FFT PLOT CHA (8192-POINT RECORD,

DIFFERENTIAL INPUT)

MAX1181 toc03

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

INA

= 19.9123MHz

INB

= 24.9123MHz

CLK

= 80.000568MHz

AINA = -0.52 dB FS

CHA

Typical Operating Characteristics

= +3V, OV

= +2.5V, internal reference, differential input at -0.5dB FS, f

CLK

= 80.0005678MHz, C

≈ 10pF. T

= +25°C,

unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Operating, f

INA or B

= 20MHz at -0.5dB FS 246 291 mW

Sleep mode 8.4Power Dissipation PDISS

Shutdown, clock idle, PD = OE = OV

345

µW

Offset ±0.2 mV/V

Power Supply Rejection PSRR

Gain ±0.1 %/V

TIMING CHARACTERISTICS

CLK Rise to Output Data Valid t

Figure 3 (Note 3) 5 8 ns

Output Enable Time t

ENABLE

Figure 4 10 ns

Output Disable Time t

DISABLE

Figure 4 1.5 ns

CLK Pulse Width High t

Figure 3 clock period: 12ns 6 ±1ns

CLK Pulse Width Low t

Figure 3 clock period: 12ns 6 ±1ns

Wakeup from sleep mode (Note 4) 0.28

Wake-Up Time t

WAKE

Wakeup from shutdown (Note 4) 1.5

µs

CHANNEL-TO-CHANNEL MATCHING

Crosstalk f

INA or B

= 20MHz at -0.5dB FS -70 dB

Gain Matching f

INA or B

= 20MHz at -0.5dB FS 0.02 ±0.2 dB

Phase Matching f

INA or B

= 20MHz at -0.5dB FS 0.25 degrees

ELECTRICAL CHARACTERISTICS (continued)

= +3V, OV

= +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through

a 10kΩ resistor, V

= 2V

p-p

(differential w.r.t. COM), C

= 10pF at digital outputs (Note 5), f

CLK

= 83.333MHz (50% duty cycle), T

MIN

to T

MAX

, unless otherwise noted. Typical values are at T

= +25°C.)

Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS, referenced to a +1.024V full-scale

input voltage range.

Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is

6dB or better, if referenced to the two-tone envelope.

Note 3: Digital outputs settle to V

, V

. Parameter guaranteed by design.

Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.

Note 5: Equivalent dynamic performance is obtainable over full OV

range with reduced C

1 2 3 4 5 6 7 8 9 10 ... 18 19

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