MAX104
±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
_______________________________________________________________________________________ 5
Note 1: Static linearity parameters are computed from a “best-fit” straight line through the code transition points. The full-scale
range (FSR) is defined as 256
· slope of the line.
Note 2: The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit
voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.
Note 3: The clock input’s termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings
on the CLK+ and CLK- inputs.
Note 4: Input logic levels are measured with respect to the V
CC
O power-supply voltage.
Note 5: All PECL digital outputs are loaded with 50Ω to V
CC
O - 2.0V. Measurements are made with respect to the V
CC
O power-
supply voltage.
Note 6: The current in the V
CC
O power supply does not include the current in the digital output’s emitter followers, which is a func-
tion of the load resistance and the V
TT
termination voltage.
Note 7: Common-Mode Rejection Ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in
the common-mode voltage, expressed in dB.
Note 8: Power-Supply Rejection Ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in
power-supply voltage, expressed in dB.
Note 9: Measured with the positive supplies tied to the same potential; V
CC
A = V
CC
D = V
CC
I. V
CC
varies from +4.75V to +5.25V.
Note 10: V
EE
varies from -5.25V to -4.75V.
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
A = V
CC
I = V
CC
D = +5.0V, V
EE
= -5.0V, V
CC
O = +3.3V, REFIN connected to REFOUT, f
S
= 1Gsps, f
IN
at -1dBFS, T
A
= +25°C,
unless otherwise noted.)
Figure 17
20% to 80%, C
L
= 3pF
20% to 80%, C
L
= 3pF
20% to 80%, C
L
= 3pF
20% to 80%, C
L
= 3pF
Figure 15
Figure 4
Figure 4
CONDITIONS
Clock
Cycles
7.5
Primary Port Pipeline
Delay
ps180t
FDREADY
DREADY Fall Time
ps220t
RDREADY
DREADY Rise Time
ps360t
FDATA
DATA Fall Time
ns0.45t
PWL
Clock Pulse Width Low
Gsps1f
MAX
Maximum Sample Rate
ps420 t
RDATA
DATA Rise Time
ps0t
SU
Reset Input Data Setup Time
(Note 13)
ps100t
AD
Aperture Delay
ps<0.5t
AJ
Aperture Jitter
UNITSMIN TYP MAXSYMBOLPARAMETER
Figure 17 ns0.45 5t
PWH
Clock Pulse Width High
Figure 15 ps0t
HD
Reset Input Data Hold Time
(Note 13)
Figure 17 ns2.2t
PD1
CLK to DREADY Propagation
Delay
Figure 17 ps-50 150 350t
PD2
DREADY to DATA Propagation
Delay (Note 14)
8.5
Figures 6, 7, 8
Clock
Cycles
9.5
t
PDA
Auxiliary Port Pipeline
Delay
t
PDP
Figures 6, 7, 8
TIMING CHARACTERISTICS
DIV1, DIV2 modes
DIV4 mode 7.5
DIV1, DIV2 modes
DIV4 mode
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