Rainbow-electronics MAX104 Manual do Utilizador Página 1

Consulte online ou descarregue Manual do Utilizador para Sensores Rainbow-electronics MAX104. Rainbow Electronics MAX104 User Manual Manual do Utilizador

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For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
General Description
The MAX104 PECL-compatible, 1Gsps, 8-bit analog-to-
digital converter (ADC) allows accurate digitizing of
analog signals with bandwidths to 2.2GHz. Fabricated
on Maxim’s proprietary advanced GST-2 bipolar
process, the MAX104 integrates a high-performance
track/hold (T/H) amplifier and a quantizer on a single
monolithic die.
The innovative design of the internal T/H, which has an
exceptionally wide 2.2GHz full-power input bandwidth,
results in high performance (greater than 7.5 effective
bits) at the Nyquist frequency. A fully differential com-
parator design and decoding circuitry reduce out-of-
sequence code errors (thermometer bubbles or sparkle
codes) and provide excellent metastable performance
of one error per 10
16
clock cycles. Unlike other ADCs
that can have errors resulting in false full- or zero-scale
outputs, the MAX104 limits the error magnitude to
1LSB.
The analog input is designed for either differential or
single-ended use with a ±250mV input voltage range.
Dual, differential, PECL-compatible output data paths
ensure easy interfacing and include an 8:16 demulti-
plexer feature that reduces output data rates to one-half
the sampling clock rate. The PECL outputs can be
operated from any supply between +3V to +5V for com-
patibility with +3.3V or +5V referenced systems. Control
inputs are provided for interleaving additional MAX104
devices to increase the effective system sampling rate.
The MAX104 is packaged in a 25mm x 25mm, 192-con-
tact Enhanced Super-Ball Grid Array (ESBGA™) and is
specified over the commercial (0°C to +70°C) tempera-
ture range.
Applications
Digital RF/IF Signal Processing
Direct RF Downconversion
High-Speed Data Acquisition
Digital Oscilloscopes
High-Energy Physics
Radar/Sonar/ECM Systems
ATE Systems
Features
1Gsps Conversion Rate
2.2GHz Full-Power Analog Input Bandwidth
>7.5 Effective Bits at f
IN
= 500MHz (Nyquist
Frequency)
±0.25LSB INL and DNL
50 Differential Analog Inputs
±250mV Input Signal Range
On-Chip, +2.5V Precision Bandgap Voltage
Reference
Latched, Differential PECL Digital Outputs
Low Error Rate: 10
-16
Metastable States at 1Gsps
Selectable 8:16 Demultiplexer
Internal Demux Reset Input with Reset Output
192-Contact ESBGA Package
MAX104
±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
________________________________________________________________
Maxim Integrated Products
1
ESBGA
TOP VIEW
MAX104
19-1459; Rev 1; 5/99
PART
MAX104CHC 0°C to +70°C
TEMP. RANGE PIN-PACKAGE
192 ESBGA
EVALUATION KIT
AVAILABLE
Typical Operating Circuit appears at end of data sheet.
192-Contact ESBGA
Ball Assignment Matrix
Ordering Information
ESBGA is a trademark of Amkor/Anam.
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Resumo do Conteúdo

Página 1 - ±5V, 1Gsps, 8-Bit ADC with

For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.For small orders, phone 1-800-835-8769.General DescriptionThe MAX104 PECL-

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Principle of OperationThe MAX104’s flash or parallel architecture providesthe fastest multibit conversion of all common integratedADC designs. The key

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MAX104REFOUT to REFIN. This connects the reference outputto the positive input of the reference buffer. The buffer’snegative input is internally conne

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Non-Demultiplexed DIV1 ModeThe MAX104 may be operated at up to 500Msps in non-demultiplexed DIV1 mode (Table 2). In this mode, theinternal demultiplex

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MAX104Decimation DIV4 ModeThe MAX104 also offers a special decimated, demulti-plexed output (Figure 8) that discards every other inputsample and outpu

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In a typical single-ended configuration, the analoginput signal (Figure 10a) enters the T/H amplifier stageat the in-phase input (VIN+), while the inv

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MAX104Offset AdjustThe MAX104 provides a control input (VOSADJ) to com-pensate for system offsets. The offset adjust input is aself-biased voltage div

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-10dBm (100mV clock signal amplitude) to +10dBm(1V clock signal amplitude). The MAX104 dynamic per-formance specifications are determined by a single-

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MAX104±5V, 1Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier2 ________________________________________________________________________________

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MAX104inputs are AC-coupled. Under this condition, connectCLKCOM to GNDI. Single-ended ECL/PECL/sine-wavedrive is also possible if the undriven clock

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Reset PipelineThe next section in the reset signal path is the resetpipeline. The purpose of this block is to add clockcycles of latency to the reset

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MAX104Reset OutputFinally, the reset signal is presented in differential PECLformat to the last block of the reset signal path.RSTOUT+/RSTOUT- output

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asserted, the auxiliary port contained “even” sampleswhile the primary port contained “odd” samples. Afterthe RSTOUT is deasserted (which marks the st

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MAX104of determining the die temperature is to measure eachcurrent with an ammeter (which shuts off the internalcatch diodes) referenced to GNDI. The

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Thermal PerformanceThe MAX104 has been modeled to determine the ther-mal resistance from junction to ambient. Table 7 lists the ADC’s thermal performa

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MAX104All supplies should be decoupled with large tantalum orelectrolytic capacitors at the point where they enter thePCB. For best performance, bypas

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Bit Error Rates (BER)Errors resulting from metastable states may occur whenthe analog input voltage (at the time the sample is taken)falls close to th

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MAX104±5V, 1Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold AmplifierMaxim cannot assume responsibility for use of any circuitry other than circuitry e

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