
79
2588B–AVR–11/06
ATtiny261/461/861
Figure 14-6. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
Figure 14-7 shows the setting of OCF0A and OCF0B in Normal mode.
Figure 14-7. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f
clk_I/O
/8)
shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.
Figure 14-8. Timer/Counter Timing Diagram, CTC mode, with Prescaler (f
clk_I/O
/8)
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
PCK
clk
Tn
(clk
PCK
/8)
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