83
8127B–AVR–08/09
ATtiny4/5/9/10
13. Analog to Digital Converter
13.1 Features
• 8-bit Resolution
• 0.5 LSB Integral Non-linearity
• ± 1 LSB Absolute Accuracy
• 65µs Conversion Time
• 15 kSPS at Full Resolution
• Four Multiplexed Single Ended Input Channels
• Input Voltage Range: 0 – V
CC
• Supply Voltage Range: 2.5V – 5.5V
• Free Running or Single Conversion Mode
• ADC Start Conversion by Auto Triggering on Interrupt Sources
• Interrupt on ADC Conversion Complete
• Sleep Mode Noise Canceler
13.2 Overview
ATtiny5/10 feature an 8-bit, successive approximation ADC. The ADC is connected to a 4-chan-
nel analog multiplexer which allows four single-ended voltage inputs constructed from the pins
of port B. The single-ended voltage inputs refer to 0V (GND).
The ADC contains a Sample-and-Hold-circuit, which ensures that the input voltage to the ADC is
held at a constant level during conversion. A block diagram of the ADC is shown in Figure 13-1
on page 84.
Internal reference voltage of V
CC
is provided on-chip.
The ADCis not available in ATtiny4/9.
13.3 Operation
In order to be able to use the ADC the Power Reduction bit, PRADC, in the Power Reduction
Register must be disabled. This is done by clearing the PRADC bit. See “PRR – Power Reduc-
tion Register” on page 26 for more details.
The ADC is enabled by setting the ADC Enable bit, ADEN in “ADCSRA – ADC Control and Sta-
tus Register A”. Input channel selections will not go into effect until ADEN is set. The ADC does
not consume power when ADEN is cleared, so it is recommended to switch off the ADC before
entering power saving sleep modes.
The ADC converts an analog input voltage to an 8-bit digital value using successive approxima-
tion. The minimum value represents GND and the maximum value represents the voltage on
V
CC
.
The analog input channel is selected by writing MUX1:0 bits. See “ADMUX – ADC Multiplexer
Selection Register” on page 93. Any of the ADC input pins can be selected as single ended
inputs to the ADC.
The ADC generates an 8-bit result which is presented in the ADC data register. See “ADCL –
ADC Data Register” on page 95.
The ADC has its own interrupt request which can be triggered when a conversion completes.
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