103
8127B–AVR–08/09
ATtiny4/5/9/10
14.5.2 SST - Serial STore to data space using indirect addressing
The SST instruction uses indirect addressing to store into data space the byte that is shifted into
the physical layer shift register. The data space location is pointed by the Pointer Register (PR),
where the address must have been stored before the operation. The Pointer Register can be
either left unchanged by the operation, or it can be post-incremented, as shown in Table 14-3.
14.5.3 SSTPR - Serial STore to Pointer Register
The SSTPR instruction stores the data byte that is shifted into the physical layer shift register to
the Pointer Register (PR). The address bit of the instruction specifies which byte of the Pointer
Register is accessed, as shown in Table 14-4.
14.5.4 SIN - Serial IN from i/o space using direct addressing
The SIN instruction loads data byte from the I/O space to the shift register of the physical layer
for serial read-out. The instuction uses direct addressing, the address consisting of the 6
address bits of the instruction, as shown in Table 14-5.
14.5.5 SOUT - Serial OUT to i/o space using direct addressing
The SOUT instruction stores the data byte that is shifted into the physical layer shift register to
the I/O space. The instruction uses direct addressing, the address consisting of the 6 address
bits of the instruction, as shown in Table 14-6.
Table 14-3. The Serial Store to Data Space (SLD) Instruction
Operation Opcode Remarks Register
DS[PR] ← data
0110 0000
PR ← PR
Unchanged
DS[PR]
← data
0110 0100
PR ← PR + 1
Post increment
Table 14-4. The Serial Store to Pointer Register (SSTPR) Instruction
Operation Opcode Remarks
PR[a] ← data
0110 100a Bit ‘a’ addresses Pointer Register byte
Table 14-5. The Serial IN from i/o space (SIN) Instruction
Operation Opcode Remarks
data ← I/O[a]
0aa1 aaaa Bits marked ‘a’ form the direct, 6-bit addres
Table 14-6. The Serial OUT to i/o space (SOUT) Instruction
Operation Opcode Remarks
I/O[a] ← data
1aa1 aaaa
Bits marked ‘a’ form the direct, 6-bit addres
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