Rainbow-electronics ATmega162V Manual do Utilizador descarregar pdf (Página 273)

100

101

273

ATmega162/V

2513E–AVR–09/03

Figure 120. External Memory Timing (SRWn1 = 1, SRWn0 = 0)

Figure 121. External Memory Timing (SRWn1 = 1, SRWn0 = 1)

(1)

Note: 1. The ALE pulse in the last period (T4 - T7) is only present if the next instruction

accesses the RAM (internal or external).

ALE

T1 T2 T3

Write

Read

A15:8

Address

Prev. addr.

DA7:0

Address DataPrev. data XX

DA7:0 (XMBK = 0)

Data

Address

System Clock (CLK

CPU

)

8 12

ALE

T1 T2 T3

Write

Read

A15:8

Address

Prev. addr.

DA7:0

Address DataPrev. data XX

DA7:0 (XMBK = 0)

Data

Address

System Clock (CLK

CPU

)

8 12

1 2 ... 268 269 270 271 272 273 274 275 276 277 278 ... 322 323

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