Rainbow-electronics ATmega103L Manual do Utilizador descarregar pdf (Página 85)

ATmega603/103

Port D Schematics

Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures.

Figure 62. Port D Schematic Diagram (Pins PD0, PD1, PD2 and PD3)

Figure 63. Port D Schematic Diagram (Pin PD4)

DATA BUS

RESET

MOS

PULL-

PDn

WP:

WD:

RL:

RP:

RD:

WRITE PORTD

WRITE DDRD

READ PORTD LATCH

READ PORTD PIN

READ DDRD

0, 1, 2, 3

DDDn

PORTDn

INTn

DATA BUS

RESET

MOS

PULL-

PD4

WP:

WD:

RL:

RP:

RD:

ACIC:

ACO:

WRITE PORTD

WRITE DDRD

READ PORTD LATCH

READ PORTD PIN

READ DDRD

COMPARATOR IC ENABLE

COMPARATOR OUTPUT

DDD4

PORTD4

NOISE CANCELER EDGE SELECT ICF1

ICNC1 ICES1

ACIC

ACO

1 2 ... 80 81 82 83 84 85 86 87 88 89 90 ... 125 126

Features 1
ATmega603/103 10
Port D Schematics 85
Memory Programming 92
Typical characteristics 110
ACTIVE SUPPLY CURRENT vs. V 111
IDLE SUPPLY CURRENT vs. V 112
COMMON MODE VOLTAGE 114
T = 85˚C 116
T = 25˚C 116
Input hysteresis (V) 120
Register Summary 121
• ($FF - K) Z,N,V 1 122
Note: 1. Not in ATmega603 123
Packaging Information 125
0945D–06/99/xM 126

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