Rainbow-electronics ATmega103L Manual do Utilizador descarregar pdf (Página 58)

ATmega603/103

•

Bit 4 - MSTR: Master/Slave Select

This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input

and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to

set MSTR to re-enable SPI master mode.

•

Bit 3 - CPOL: Clock Polarity

When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 39

and Figure 40 for additional information.

•

Bit 2 - CPHA: Clock Phase

Refer to Figure 39 or Figure 40 for the functionality of this bit.

•

Bits 1,0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. The

relationship between SCK and the CPU Clock frequency f

is shown in the following table:

Note: Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled.

SPI Status Register - SPSR

•

Bit 7 - SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and

global interrupts are enabled. SPIF is cleared by hardware when executing the corresponding interrupt handling vector.

Alternatively, the SPIF bit is cleared by first reading the SPI status register with SPIF set (one), then accessing the SPI

Data Register (SPDR).

•

Bit 6 - WCOL: Write Collision flag

The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are

cleared (zero) by first reading the SPI Status Register with WCOL set (one), and then accessing the SPI Data Register.

•

Bit 5..0 - Res: Reserved bits

These bits are reserved bits in the ATmega603/103 and will always read as zero.

SPI Data Register - SPDR

The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register.

Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.

Table 24. Relationship Between SCK and the Oscillator Frequency

SPR1 SPR0 SCK Frequency

/ 4

/ 16

/ 64

/ 128

Bit 76543210

$0E SPIF WCOL - - - - - - SPSR

Read/WriteRRRRRRRR

Initial value00000000

Bit 76543210

$0F ($2F) MSB LSB SPDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value

XXXXXXXXUndefined

1 2 ... 53 54 55 56 57 58 59 60 61 62 63 ... 125 126

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