Rainbow-electronics DS3134 Manual do Utilizador Página 5
- Página / 203
- Índice
- MARCADORES
Avaliado. / 5. Com base em avaliações de clientes
DS3134
5 of 203
TABLE OF CONTENTS
Section 1: Introduction……………………………………………………………………………………..7
Section 2: Signal Description…………………………………………………………………………… 16
2.1 Overview / Signal Lead List………………………………………………………………… 16
2.2 Serial Port Interface Signal Description…………………………………………………… 22
2.3 Local Bus Signal Description………………………………………………………………. 24
2.4 JTAG Signal Description…………………………………………………………………… 27
2.5 PCI Bus Signal Description………………………………………………………………… 28
2.6 Supply & Test Signal Description…………………...…………………………………….. 31
Section 3: Memory Map………………………………………………………………………………… 32
3.0 Introduction………………………………………………………………………………….. 32
3.1 General Configuration Registers………………………………………………………….. 32
3.2 Receive Port Registers…………………………………………………………………….. 33
3.3 Transmit Port Registers……………………………………………………………………. 33
3.4 Channelized Port Registers……………………………………………………………….. 34
3.5 HDLC Registers……………………………………………………………………………. 35
3.6 BERT Registers…………………………………………………………………………….. 35
3.7 Receive DMA Registers……………………………………………………………………. 35
3.8 Transmit DMA Registers…………………………………………………………………… 36
3.9 FIFO Registers……………………………………………………………………………… 36
3.10 PCI Configuration Registers for Function 0……………………………………………. 36
3.11 PCI Configuration Registers for Function 1……………………………………………. 37
Section 4: General Device Configuration & Status/Interrupt………………………………………….. 37
4.1 Master Reset & ID Register Description…………………………………………………. 37
4.2 Master Configuration Register Description………………………………………………. 38
4.3 Status & Interrupt…………………………………………………………………………… 40
4.3.1 Status & Interrupt General Description……………………………………… 40
4.3.2 Status & Interrupt Register Description……………………………………… 43
4.4 Test Register Description………………………………………………………………….. 50
Section 5: Layer One…………………………………………………………………………………… 51
5.1 General Description………………………………………………………………………… 51
5.2 Port Register Description………………………………………………………………….. 55
5.3 Layer One Configuration Register Description………………………………………….. 59
5.4 Receive V.54 Detector…………………………………………………………………….. 65
5.5 BERT…………………………………………………………………………………………69
5.6 BERT Register Description……………………………………………………………….. 70
Section 6: HDLC…………………………………………………………………………………………77
6.1 General Description……………………………………………………………………….. 77
6.2 HDLC Register Description………………………………………………………………. 79
- Chateau – Channelized T 1
- E1 And HDLC Controller 1
- REVISION HISTORY 3
- TABLE OF CONTENTS 5
- SECTION 1: INTRODUCTION 7
- JTAG TEST ACCESS 9
- GENERAL DESCRIPTION 10
- INITIALIZATION 14
- INDIRECT REGISTERS Table 1E 15
- SECTION 2: SIGNAL DESCRIPTION 16
- RS SAMPLED EDGE Table 2.2A 23
- TS SAMPLED EDGE Table 2.2B 23
- 2.4 JTAG SIGNAL DESCRIPTION 27
- SECTION 3: MEMORY MAP 33
- 3.0 INTRODUCTION 33
- 3.5 HDLC REGISTERS (4XX) 35
- 3.6 BERT REGISTERS (5XX) 36
- 3.9 FIFO REGISTERS (9XX) 37
- 4.3 STATUS & INTERRUPT 41
- SM Register 42
- SV54 Register 42
- SDMA Register 42
- 43 of 203 43
- 4.4 TEST REGISTER DESCRIPTION 51
- SECTION 5: LAYER ONE 52
- 5.1 GENERAL DESCRIPTION 52
- 54 of 203 54
- Figure 5.1B 55
- 5.4 RECEIVE V.54 DETECTOR 66
- 68 of 203 68
- 69 of 203 69
- 5.5 BERT 70
- BERT Mux Diagram Figure 5.5A 70
- Repetitive Pattern Length Map 73
- SECTION 6: HDLC 78
- 6.1 GENERAL DESCRIPTION 78
- SECTION 7: FIFO 86
- FIFO Example Figure 7.1A 87
- Transmit Low Water Mark 88
- Receive High Water Mark 88
- SECTION 8: DMA 96
- 8.0 INTRODUCTION 96
- 8.1 RECEIVE SIDE 98
- 8.1.1 OVERVIEW 98
- Receive DMA Actions 100
- Host Actions 100
- 101 of 203 101
- 102 of 203 102
- 8.1.2 PACKET DESCRIPTORS 103
- 8.1.3 FREE QUEUE 105
- Status / Interrupts 109
- Free Queue Burst Reading 109
- 8.1.4 DONE QUEUE 110
- Empty Case 112
- Full Case 112
- Receive Done Queue Full State 112
- Status Bits / Interrupts 114
- Done Queue Burst Writing 114
- Done Queue FIFO Flush Timer 115
- - HOST MUST CONFIGURE 118
- 8.2 TRANSMIT SIDE 120
- 8.2.1 OVERVIEW 120
- Host Linking of Data Buffers 121
- Priority Packets 122
- 123 of 203 123
- 124 of 203 124
- 125 of 203 125
- 126 of 203 126
- DMA UPDATES TO THE DONE QUEUE 127
- ERROR CONDITIONS 127
- Transmit DMA Actions 128
- 8.2.2 Packet Descriptors 129
- the Transmit Descriptor 130
- the Transmit 130
- 8.2.3 PENDING QUEUE 131
- Empty Case 132
- Pending Queue Burst Reading 134
- 8.2.4 DONE QUEUE 135
- SECTION 9: PCI BUS 145
- PCI Read Cycle 146
- PCI Bus Read Figure 9.1B 146
- PCI Write Cycle 147
- PCI Bus Write Figure 9.1C 147
- PCI Bus Arbitration 148
- PCI Initiator Abort 148
- PCI Target Retry 149
- PCI Target Retry Figure 9.1F 149
- PCI Target Disconnect 149
- PCI Target Abort 150
- PCI Target Abort Figure 9.1H 150
- PCI Fast Back-to-Back 150
- COMMAND BITS 152
- STATUS BITS 153
- SECTION 10: LOCAL BUS 163
- Bridge Mode Figure 10.1A 164
- PCI Bridge Mode 165
- Bridge Mode Bus Arbitration 167
- Bridge Mode Interrupt 167
- Configuration Mode 167
- 168 of 203 168
- 03/22/99 173
- 192 of 203 192
- 194 of 203 194
- 195 of 203 195
- 198 of 203 198
Manuais e produtos relacionados com Comunicação Rainbow-electronics DS3134
(69 páginas)© 2020, manymanuals-pt.com. Todos os direitos reservados. | 0.055 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentários a estes Manuais