Rainbow-electronics DS2151Q Manual do Utilizador

Copyright 1995 by Dallas Semiconductor Corporation.All Rights Reserved. For important information regardingpatents and other intellectual property r

DS2151Q022697 10/46TLINK TCR1.2 TLINK Select. (see note below) 0=source FDL or Fs bits from TFDL register 1=source FDL or Fs bits from the TLINK pinT

DS2151Q022697 11/46CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex)(MSB) (LSB)TESE LLB RSAO RLB SCLKM RESE PLB FLBSYMBOL POSITION NAME AND DESCRIPTION

DS2151Q022697 12/46DS2151Q. When PLB is enabled, the following willoccur:1. data will be transmitted from the TTIP and TRINGpins synchronous with RCL

DS2151Q022697 13/46CCR3: COMMON CONTROL REGISTER 3 (Address=30 Hex)(MSB) (LSB)ESMDM ESR P16F RSMS PDE TLD TLU LIRSTSYMBOL POSITION NAME AND DESCRIPTIO

DS2151Q022697 14/46When the CCR3.3 is set to one, the DS2151Q will forcethe transmitted stream to meet this requirement no mat-ter the content of the

DS2151Q022697 15/46RESE RIR1.3 Receive Elastic Store Empty. Set when the receive elastic store bufferempties and a frame is repeated.SEFE RIR1.2 Seve

DS2151Q022697 16/46SR1: STATUS REGISTER 1 (Address=20 Hex)(MSB) (LSB)LUP LDN LOTC RSLIP RBL RYEL RCL RLOSSYMBOL POSITION NAME AND DESCRIPTIONLUP SR1.7

DS2151Q022697 17/46LOOP UP/DOWN CODE DETECTIONBits SR1.7 and SR1.6 will indicate when either the stan-dard “loop up” or “loop down” codes are being re

DS2151Q022697 18/46SLIP IMR1.4 Elastic Store Slip Occurrence. 0=interrupt masked 1=interrupt enabledRBL IMR1.3 Receive Blue Alarm. 0=interrupt masked

DS2151Q022697 19/465.0 ERROR COUNT REGISTERSThere are a set of three counters in the DS2151Q thatrecord bipolar violations, excessive zeros, errors in

DS2151Q022697 2/46or 128 bits) can be placed in either the transmit orreceive data paths. The framer locates the frame andmultiframe boundaries and m

DS2151Q022697 20/46PCVCR1: PATH VIOLATION COUNT REGISTER 1 (Address=25 Hex)PCVCR2: PATH VIOLATION COUNT REGISTER 2 (Address=26 Hex)(MSB) (LSB)(note 1)

DS2151Q022697 21/46NOTES:1. The lower nibble of the counter at address 25 is used by the Path Code Violation Count Register.2. MOSCR counts either err

DS2151Q022697 22/46RFDLM1: RECEIVE FDL MATCH REGISTER 1 (Address=29 Hex)RFDLM2: RECEIVE FDL MATCH REGISTER 2 (Address=2A Hex)(MSB) (LSB)RFDL7 RFDL6 RF

DS2151Q022697 23/467.0 SIGNALING OPERATIONThe Robbed–Bit signaling bits embedded in the T1stream can be extracted from the receive stream andinserted

DS2151Q022697 24/46TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (Address=70 to 7B Hex) (MSB) (LSB)A(8)A(7) A(6) A(5) A(4) A(3) A(2) A(1)A(16) A(15) A(

DS2151Q022697 25/46TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTERS (Address=39 to 3B Hex) (MSB) (LSB)CH8CH7 CH6 CH5 CH4 CH3 CH2 CH1CH16 CH15 CH14 C

DS2151Q022697 26/46made transparent by the Transmit Transparency Regis-ters.9.0 CLOCK BLOCKING REGISTERSThe Receive Channel Blocking Registers(RCBR1/R

DS2151Q022697 27/46boundary, then RCR2.4 must be set to one. If the userselects to apply a 2.048 MHz clock to the SYSCLK pin,then the data output at

DS2151Q022697 28/4612.0 LINE INTERFACE FUNCTIONSThe line interface function in the DS2151Q containsthree sections; (1) the receiver which handles cloc

DS2151Q022697 29/46clock is applied to the ACLKI pin, then it should be tied toRVSS to prevent the device from falsely sensing aclock. See Table 12–1

BPV COUNTERSYNCHRONIZERALARM DETECTIONLOOP CODE DETECTORCRC/FRAME ERROR COUNTONE’S DENSITY MONITORSIGNALING EXTRACTIONPAYLOAD LOOPBACKELASTICSTORERECE

DS2151Q022697 30/46TRANSFORMER SPECIFICATIONS Table 12–3SPECIFICATION RECOMMENDED VALUETurns Ratio 1:1 (receive) and 1:1.15 or 1:1.36 (transmit) ±5%P

DS2151Q022697 31/46DS2151Q EXTERNAL ANALOG CONNECTIONS Figure 12–1+5V+68 µF0.1 µF0.1 µF0.1 µF6.176 MHzDVDDDVSSRVDDRVSSTVDDTVSSXTAL1XTAL2TTIPTRINGRTIPR

1 10 100 1K 10K 100KFREQUENCY (Hz)0 dB–20 dB–40 dB–60 dBJITTER ATTENUATION (dB)TR 62411 (DEC. 90)PROHIBITEDAREADS2151Q022697 32/46DS2151Q TRANSMIT WAV

DS2151Q022697 33/4613.0 TIMING DIAGRAMSRECEIVE SIDE D4 TIMING Figure 13–112 345 67891011121 23 45FRAME#RSYNC1RSYNC2RSYNC3RLCLKRLINK4NOTES:1. RSYNC in

DS2151Q022697 34/46RECEIVE SIDE BOUNDARY TIMING WITH ELASTIC STORE(S) DISABLED Figure 13–3RCLKRSERRSYNCRCHCLKRCHBLK1RLCLKRLINKLSB MSB LSB MSBFCHANNEL

DS2151Q022697 35/461.544 MHz BOUNDARY TIMING WITH ELASTIC STORE(S) ENABLED Figure 13–4SYSCLKTSER/RSERRSYNC1RSYNC2RCHCLKRCHBLK3CHANNEL 24 CHANNEL 1CHAN

DS2151Q022697 36/46TRANSMIT SIDE D4 TIMING Figure 13–61 2 34 567891011121 234 5FRAME#TSYNC1TSYNC2TSYNC3TLCLKTLINK4NOTES:1. TSYNC in the frame mode (TC

DS2151Q022697 37/465. TLINK data (FDL bits) is sampled during the F-bit time of odd frame and inserted into the outgoing T1 stream ifenabled via TCR1.

KEY= REGISTER= DEVICE PIN= SELECTORTSERTIDRIDLE CODE MUXTIR1 TO TIR3TS1 TO TS12SIGNALING MUXBIT 7 STUFFINGLOOP CODE GENERATIOND4 BIT 2 YELLOWALARM INS

DS2151Q022697 39/46ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground –1.0V to +7.0VOperating Temperature 0°C to +70°C (–40°C to +85°C for

DS2151Q022697 4/46PIN DESCRIPTION Table 1–1PIN SYMBOL TYPE DESCRIPTION1234AD4AD5AD6AD7I/O Address/Data Bus. An 8–bit multiplexed address/data bus.5

ALEWRRDCSAD0-AD7tCYCPWASHPWEHtASDtASEDtASLtDDRtCHtDHRtASDtCStAHLPWELDS2151Q022697 40/46AC CHARACTERISTICS - PARALLEL PORT (0°C to 70°C; VDD=5V + 5%)(–

DS2151Q022697 41/46INTEL BUS WRITE AC TIMINGALEWRRDCSAD0-AD7PWASHtASDtASLtCHtAHLtASDtASEDPWEHPWELtDSWtDHWtCStCYCMOTOROLA BUS AC TIMINGASDSR/WAD0-AD7(R

DS2151Q022697 42/46AC CHARACTERISTICS – RECEIVE SIDE (0°C to 70°C; VDD=5V ± 5%)(–40°C to +85°C for DS2151QN)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESAC

DS2151Q022697 43/46RECEIVE SIDE AC TIMINGRCLKRSERRCHCLKRCHBLKRSYNC1RSYNC2RLCLKRLINKtD5tCLtCHtCPtSUtD4tPWtD3tD2tDDF–BIT OR MSBSYSCLKtRtFtSLtSHtSPOF CHA

DS2151Q022697 44/46AC CHARACTERISTICS – TRANSMIT SIDE (0°C to 70°C; VDD=5V + 5%)(–40°C to +85°C for DS2151QN)PARAMETER SYMBOL MIN TYP MAX UNITS NOTEST

DS2151Q022697 45/46TRANSMIT SIDE AC TIMINGTCLKTSER3TCHCLKTCHBLKTSYNC1TSYNC2TLCLKTLINKtRtFtCLtPtCHtSUtHDtD1tD2tD3tPWtSUtD4tHDtSUF–BITNOTES:1. TSYNC is

DS2151Q022697 46/46DS2151Q T1 CONTROLLER 44–PIN PLCCCA1A2 ABB1.075 MAXN1.150MAXNOTE 1D1DCH1EE1e1E2D2NOTE1: PIN 1 IDENTIFIER TO BE LOCATED IN ZONE IND

DS2151Q022697 5/46PIN DESCRIPTIONTYPESYMBOL20 BTS I Bus Type Select. Strap high to select Motorola bus timing; strap low toselect Intel bus timing.

DS2151Q022697 6/46PIN DESCRIPTIONTYPESYMBOL40 TCHCLK O Transmit Channel Clock. 192 KHz clock which pulses high during the LSBof each channel. Useful

DS2151Q022697 7/4663 R Receive Signaling Register 4. 73 R/W Transmit Signaling Register 4.64 R Receive Signaling Register 5. 74 R/W Transmit Signaling

DS2151Q022697 8/46RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex)(MSB) (LSB)LCVCRF ARC OOF1 OOF2 SYNCC SYNCT SYNCE RESYNCSYMBOL POSITION NAME AND DE

DS2151Q022697 9/46RSDW RCR2.5 RSYNC Double–Wide. 0=do not pulse double–wide in signaling frames 1=do pulse double–wide in signaling frames (note: this