Rainbow-electronics DS3170 Manual do Utilizador

1 of 233 REV: 101404 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple rev

DS3170 DS3/E3 Single-Chip Transceiver 10 of 233 LIST OF TABLES Table 4-1. Standards Compliance ...

DS3170 DS3/E3 Single-Chip Transceiver 100 of 233 The Trail Trace Controller extracts/inserts E3-G.832 trail access point identifiers using a 16-byt

DS3170 DS3/E3 Single-Chip Transceiver 101 of 233 order they are received, 1 (MSB) to 8 (LSB). However, when a byte is stored in a register, the MSB

DS3170 DS3/E3 Single-Chip Transceiver 102 of 233 Figure 9-21. Trail Trace Byte (DT = Trail Trace Data) Bit 1 MSB Bit 2 Bit 3 Bit 4 Bit 5 Bit 6

DS3170 DS3/E3 Single-Chip Transceiver 103 of 233 The transmit direction inputs codewords from the microprocessor via the register interface and sto

DS3170 DS3/E3 Single-Chip Transceiver 104 of 233 have both been sent ten times, all ones are output. In continuous mode, the code from TFCA[5:0] is

DS3170 DS3/E3 Single-Chip Transceiver 105 of 233 Figure 9-24. Line Encoder/Decoder Block Diagram DS3/E3TransmitLIUIEEE P1149.1JTAG TestAccess PortM

DS3170 DS3/E3 Single-Chip Transceiver 106 of 233 as the values for the first one. The third bipolar one is generated according to the normal AMI ru

DS3170 DS3/E3 Single-Chip Transceiver 107 of 233 Figure 9-25. B3ZS Signatures RLCLKRPOSRNEG(RX DATA)B3ZS SIGNATURE WHENLINE.RCR.RZSF = 0VRLCLKRPOSR

DS3170 DS3/E3 Single-Chip Transceiver 108 of 233 9.11 BERT 9.11.1 General Description The BERT is a software programmable test pattern generator a

DS3170 DS3/E3 Single-Chip Transceiver 109 of 233 Table 9-31. Pseudo-Random Pattern Generation BERT.PCR Register BERT.CR PATTERN TYPE PTF[4:0] (hex)

DS3170 DS3/E3 Single-Chip Transceiver 11 of 233 Table 11-19. FEAC Receive Side Register Map ...

DS3170 DS3/E3 Single-Chip Transceiver 110 of 233 then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the i

DS3170 DS3/E3 Single-Chip Transceiver 111 of 233 Figure 9-29. Repetitive Pattern Synchronization State Diagram SyncMatchVerify1 bit errorPattern Ma

DS3170 DS3/E3 Single-Chip Transceiver 112 of 233 9.12 LIU – Line Interface Unit 9.12.1 General Description The line interface units (LIUs) perform

DS3170 DS3/E3 Single-Chip Transceiver 113 of 233 waveforms onto 75W coaxial cable. Refer to Figure 9-31 for a detailed functional block diagram of

DS3170 DS3/E3 Single-Chip Transceiver 114 of 233 9.12.4.3 Interfacing to the Line The transmitter interfaces to the outgoing DS3/E3 coaxial cabl

DS3170 DS3/E3 Single-Chip Transceiver 115 of 233 Table 9-34. Recommended Transformers MANUFACTURER PART TEMP RANGE PIN-PACKAGE/ SCHEMATIC OCL PRIMA

DS3170 DS3/E3 Single-Chip Transceiver 116 of 233 The ALOS detector in the AGC/equalizer block detects that the incoming signal is less than or equa

DS3170 DS3/E3 Single-Chip Transceiver 117 of 233 10 OVERALL REGISTER MAP The register addresses of the global, test and the port are concatenated t

DS3170 DS3/E3 Single-Chip Transceiver 118 of 233 Address offset Description 08C – 08F B3ZS/HDB3 transmit line encoder 090 – 09F B3ZS/HDB3 receive

DS3170 DS3/E3 Single-Chip Transceiver 119 of 233 11 REGISTER MAPS AND DESCRIPTIONS 11.1 Registers Bit Maps Note: In 8-bit mode, register bits[15:

DS3170 DS3/E3 Single-Chip Transceiver 12 of 233 2 APPLICATIONS · Access Concentrators · Multiservice Access Platforms · ATM and Frame Relay Equi

DS3170 DS3/E3 Single-Chip Transceiver 120 of 233 Address Register Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 16-bit 8-bit Bit

DS3170 DS3/E3 Single-Chip Transceiver 121 of 233 Address Register Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 16-bit 8-bit Bit

DS3170 DS3/E3 Single-Chip Transceiver 122 of 233 Address Register Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 16-bit 8-bit Bit

DS3170 DS3/E3 Single-Chip Transceiver 123 of 233 Table 11-7. Trail Trace Register Bit Map Address Register Type Bit 7 Bit 6 Bit 5 Bit 4 Bit

DS3170 DS3/E3 Single-Chip Transceiver 124 of 233 Address Register Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 16-bit 8-bit Bit

DS3170 DS3/E3 Single-Chip Transceiver 125 of 233 Address Register Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 16-bit 8-bit Bit

DS3170 DS3/E3 Single-Chip Transceiver 126 of 233 11.2 Global Registers Table 11-11. Global Register Map Address Register Register Description 00

DS3170 DS3/E3 Single-Chip Transceiver 127 of 233 Register Name: GL.CR1 Register Description: Global Control Register 1 Register Address: 002h Bit

DS3170 DS3/E3 Single-Chip Transceiver 128 of 233 Register Name: GL.CR2 Register Description: Global Control Register 2 Register Address: 004h Bit

DS3170 DS3/E3 Single-Chip Transceiver 129 of 233 Register Name: GL.GIOCR Register Description: Global General Purpose IO Control Register Register

DS3170 DS3/E3 Single-Chip Transceiver 13 of 233 3 FEATURE DETAILS The following sections describe the features provided by the DS3170 SCT. 3.1 Glob

DS3170 DS3/E3 Single-Chip Transceiver 130 of 233 Bits 1 to 0: General Purpose IO 1 Select [1:0] (GPIO1S[1:0]). These bits determine the function o

DS3170 DS3/E3 Single-Chip Transceiver 131 of 233 Register Name: GL.SR Register Description: Global Status Register Register Address: 014h Bit # 1

DS3170 DS3/E3 Single-Chip Transceiver 132 of 233 Register Name: GL.SRIE Register Description: Global Status Register Interrupt Enable Register Add

DS3170 DS3/E3 Single-Chip Transceiver 133 of 233 11.3 Port Register 11.3.1 Register Bit Descriptions Table 11-12. Port Register Map Address Regi

DS3170 DS3/E3 Single-Chip Transceiver 134 of 233 Register Name: PORT.CR1 Register Description: Port Control Register 1 Register Address: 040h Bit

DS3170 DS3/E3 Single-Chip Transceiver 135 of 233 1 = Transmit BERT logic enabled Bit 7: Transmit Manual Error Insert (TMEI) This bit is used to i

DS3170 DS3/E3 Single-Chip Transceiver 136 of 233 0 = TXP and TXN driven 1 = TXP and TXN tri-stated Bit 13: Receive LIU Monitor Mode (RMON) This

DS3170 DS3/E3 Single-Chip Transceiver 137 of 233 Register Name: PORT.CR3 Register Description: Port Control Register 3 Register Address: 044h Bit

DS3170 DS3/E3 Single-Chip Transceiver 138 of 233 Bit 2: Receive Framer IO Signal Timing Select (RFTS). This bit controls the timing reference for

DS3170 DS3/E3 Single-Chip Transceiver 139 of 233 Table 9-16. GPIO Port Alarm Monitor Select PORT.CR4 GPIO(A/B)[3:0] LINE LOS DS3/E3 OOF DS3/E3 L

DS3170 DS3/E3 Single-Chip Transceiver 14 of 233 3.5 Transmit DS3/E3 Formatter Features § Frame insertion for M23 and C-bit parity DS3, G.751 E3 a

DS3170 DS3/E3 Single-Chip Transceiver 140 of 233 Register Name: PORT.INV1 Register Description: Port IO Invert Control Register 1 Register Address:

DS3170 DS3/E3 Single-Chip Transceiver 141 of 233 Register Name: PORT.ISR Register Description: Port Interrupt Status Register Register Address: 0

DS3170 DS3/E3 Single-Chip Transceiver 142 of 233 Bit 1: Receive Loss Of Lock Status (RLOL) This bits indicates the status of the receive LIU clock

DS3170 DS3/E3 Single-Chip Transceiver 143 of 233 Bit 1: Receive Loss Of Lock Latched Status Interrupt Enable (RLOLIE) The interrupt pin will be dri

DS3170 DS3/E3 Single-Chip Transceiver 144 of 233 11.4 BERT 11.4.1 BERT Register Map The BERT utilizes twelve registers. Table 11-13. BERT Regist

DS3170 DS3/E3 Single-Chip Transceiver 145 of 233 must be changed to zero and back to one for another pattern to be loaded. Loading a new pattern wi

DS3170 DS3/E3 Single-Chip Transceiver 146 of 233 Register Name: BERT.SPR1 Register Description: BERT Seed/Pattern Register #1 Register Address: 064

DS3170 DS3/E3 Single-Chip Transceiver 147 of 233 TEIR[2:0] Error Rate 000 Disabled 001 1*10-1 010 1*10-2 011 1*10-3 100 1*10-4 101 1*10-5 110 1*10

DS3170 DS3/E3 Single-Chip Transceiver 148 of 233 Register Name: BERT.SRL Register Description: BERT Status Register Latched Register Address: 06Eh

DS3170 DS3/E3 Single-Chip Transceiver 149 of 233 Register Name: BERT.RBECR1 Register Description: BERT Receive Bit Error Count Register #1 Register

DS3170 DS3/E3 Single-Chip Transceiver 15 of 233 3.10 Trail Trace Buffer Features § Extraction and storage of the incoming G.832 trail access poin

DS3170 DS3/E3 Single-Chip Transceiver 150 of 233 Register Name: BERT.RBCR1 Register Description: Receive Bit Count Register #1 Register Address: 07

DS3170 DS3/E3 Single-Chip Transceiver 151 of 233 11.5 B3ZS/HDB3 Line Encoder/Decoder 11.5.1 Transmit Side Line Encoder/Decoder Register Map The

DS3170 DS3/E3 Single-Chip Transceiver 152 of 233 11.5.2 Receive Side Line Encoder/Decoder Register Map The receive side utilizes six registers. T

DS3170 DS3/E3 Single-Chip Transceiver 153 of 233 Bit 0: Receive Zero Suppression Decoding Disable (RZSD) – When 0, the B3ZS/HDB3 Decoder performs z

DS3170 DS3/E3 Single-Chip Transceiver 154 of 233 Register Name: LINE.RSRIE Register Description: Line Receive Status Register Interrupt Enable Regi

DS3170 DS3/E3 Single-Chip Transceiver 155 of 233 Register Name: LINE.REXZCR Register Description: Line Receive Excessive Zero Count Register Regis

DS3170 DS3/E3 Single-Chip Transceiver 156 of 233 11.6 HDLC 11.6.1 HDLC Transmit Side Register Map The transmit side utilizes five registers. Tab

DS3170 DS3/E3 Single-Chip Transceiver 157 of 233 Bit 1: Transmit FCS Processing Disable (TFPD) – This bit controls whether or not an FCS is calcula

DS3170 DS3/E3 Single-Chip Transceiver 158 of 233 Register Name: HDLC.TSRL Register Description: HDLC Transmit Status Register Latched Register Ad

DS3170 DS3/E3 Single-Chip Transceiver 159 of 233 Bit 2: Transmit FIFO Full Interrupt Enable (TFFIE) – This bit enables an interrupt if the TFFL bit

DS3170 DS3/E3 Single-Chip Transceiver 16 of 233 4 STANDARDS COMPLIANCE Table 4-1. Standards Compliance SPECIFICATION SPECIFICATION TITLE ANSI T1.

DS3170 DS3/E3 Single-Chip Transceiver 160 of 233 Bit 0: Receive FIFO Reset (RFRST) – When 0, the Receive FIFO will resume normal operations, howeve

DS3170 DS3/E3 Single-Chip Transceiver 161 of 233 Register Name: HDLC.RSRIE Register Description: HDLC Receive Status Register Interrupt Enable Regi

DS3170 DS3/E3 Single-Chip Transceiver 162 of 233 Bits 3 to 1: Receive Packet Status (RPS[2:0]) – These three bits indicate the status of the receiv

DS3170 DS3/E3 Single-Chip Transceiver 163 of 233 11.7 FEAC Controller 11.7.1 FEAC Transmit Side Register Map The transmit side utilizes five regis

DS3170 DS3/E3 Single-Chip Transceiver 164 of 233 Register Name: FEAC.TFDR Register Description: Transmit FEAC Data Register Register Address: 0C2h

DS3170 DS3/E3 Single-Chip Transceiver 165 of 233 Register Name: FEAC.TSRIE Register Description: FEAC Transmit Status Register Interrupt Enable Reg

DS3170 DS3/E3 Single-Chip Transceiver 166 of 233 Register Name: FEAC.RSR Register Description: FEAC Receive Status Register Register Address: 0D4h

DS3170 DS3/E3 Single-Chip Transceiver 167 of 233 Bit 1: Receive FEAC Codeword Detect Interrupt Enable (RFCDIE) – This bit enables an interrupt if t

DS3170 DS3/E3 Single-Chip Transceiver 168 of 233 11.8 Trail Trace 11.8.1 Trail Trace Transmit Side The transmit side utilizes three registers. T

DS3170 DS3/E3 Single-Chip Transceiver 169 of 233 Register Name: TT.TTIAR Register Description: Trail Trace Transmit Identifier Address Register Re

DS3170 DS3/E3 Single-Chip Transceiver 17 of 233 5 ACRONYMS AND GLOSSARY Definition of the terms used in this data sheet: · CCM—Clear-Channel Mode

DS3170 DS3/E3 Single-Chip Transceiver 170 of 233 11.8.2.1 Register Bit Descriptions Register Name: TT.RCR Register Description: Trail Trace Recei

DS3170 DS3/E3 Single-Chip Transceiver 171 of 233 Register Name: TT.RSR Register Description: Trail Trace Receive Status Register Register Address:

DS3170 DS3/E3 Single-Chip Transceiver 172 of 233 Register Name: TT.RSRIE Register Description: Trail Trace Receive Status Register Interrupt Enable

DS3170 DS3/E3 Single-Chip Transceiver 173 of 233 Register Name: TT.EIR Register Description: Trail Trace Expected Identifier Register Register Addr

DS3170 DS3/E3 Single-Chip Transceiver 174 of 233 11.9 DS3/E3 framer 11.9.1 Transmit DS3 The transmit DS3 utilizes two registers. Table 11-22. T

DS3170 DS3/E3 Single-Chip Transceiver 175 of 233 Bit 1: Transmit Frame Generation Disabled (TFGD) – 0 = Transmit Frame Generation is enabled 1 =

DS3170 DS3/E3 Single-Chip Transceiver 176 of 233 Bit 0: Manual Error Insert Mode Select (MEIMS) – When 0, error insertion is initiated by the TSEI

DS3170 DS3/E3 Single-Chip Transceiver 177 of 233 Bit 11: Automatic Downstream AIS Disable (AAISD) – When 0, the presence of an LOS, OOF, or AIS con

DS3170 DS3/E3 Single-Chip Transceiver 178 of 233 Bit 10: Application Identification Channel (AIC) – This bit indicates the current state of the Ap

DS3170 DS3/E3 Single-Chip Transceiver 179 of 233 Register Name: T3.RSRL1 Register Description: T3 Receive Status Register Latched #1 Register Addre

DS3170 DS3/E3 Single-Chip Transceiver 18 of 233 6 MAJOR OPERATIONAL MODES The major operational modes are determined by the FM[2:0] framer mode bit

DS3170 DS3/E3 Single-Chip Transceiver 180 of 233 Bit 2: Remote Error Indication Count Latched (FBECL) – This bit is set when the FBEC bit transitio

DS3170 DS3/E3 Single-Chip Transceiver 181 of 233 Bit 3: Remote Defect Indication Interrupt Enable (RDIIE) – This bit enables an interrupt if the RD

DS3170 DS3/E3 Single-Chip Transceiver 182 of 233 Bit 2: Far-End Block Error Count Interrupt Enable (FBECIE) – This bit enables an interrupt if the

DS3170 DS3/E3 Single-Chip Transceiver 183 of 233 Register Name: T3.RFBECR Register Description: T3 Receive Far-End Block Error Count Register Regis

DS3170 DS3/E3 Single-Chip Transceiver 184 of 233 11.9.3.2 Register Bit Descriptions Register Name: E3G751.TCR Register Description: E3 G.751 Trans

DS3170 DS3/E3 Single-Chip Transceiver 185 of 233 Register Name: E3G751.TEIR Register Description: E3 G.751 Transmit Error Insertion Register Regist

DS3170 DS3/E3 Single-Chip Transceiver 186 of 233 11.9.4 Receive G.751 E3 Register Map The receive G.751 E3 utilizes eight registers. Table 11-25.

DS3170 DS3/E3 Single-Chip Transceiver 187 of 233 Bits 9 to 8: Framing Error Count Control (FECC[1:0]) – These two bits control the type of framing

DS3170 DS3/E3 Single-Chip Transceiver 188 of 233 Bit 1: Out Of Frame (OOF) – When 0, the receive frame processor is not in an out of frame (OOF) co

DS3170 DS3/E3 Single-Chip Transceiver 189 of 233 Register Name: E3G751.RSRL2 Register Description: E3 G.751 Receive Status Register Latched #2 Regi

DS3170 DS3/E3 Single-Chip Transceiver 19 of 233 Figure 6-1. DS3/E3 Framed LIU Mode TSOFO/TDENRLCLKRXPRXNTPOS/TDATTNEGTLCLKDS3/E3TransmitLIUIEEE P11

DS3170 DS3/E3 Single-Chip Transceiver 190 of 233 Bit 2: Alarm Indication Signal Interrupt Enable (AISIE) – This bit enables an interrupt if the AIS

DS3170 DS3/E3 Single-Chip Transceiver 191 of 233 11.9.5 Transmit G.832 E3 Register Map The transmit G.832 E3 utilizes four registers. Table 11-2

DS3170 DS3/E3 Single-Chip Transceiver 192 of 233 1 = Transmit Frame Generation is disabled; E3 overhead positions in the incoming E3 payload will b

DS3170 DS3/E3 Single-Chip Transceiver 193 of 233 Register Name: E3G832.TMABR Register Description: E3 G.832 Transmit MA Byte Register Register Addr

DS3170 DS3/E3 Single-Chip Transceiver 194 of 233 11.9.6 Receive G.832 E3 Register Map The receive G.832 E3 utilizes thirteen registers. Table 11-

DS3170 DS3/E3 Single-Chip Transceiver 195 of 233 Bits 9 to 8: Framing Error Count Control (FECC[1:0]) – These two bits control the type of framing

DS3170 DS3/E3 Single-Chip Transceiver 196 of 233 Register Name: E3G832.RSR1 Register Description: E3 G.832 Receive Status Register #1 Register Addr

DS3170 DS3/E3 Single-Chip Transceiver 197 of 233 Register Name: E3G832.RSRL1 Register Description: E3 G.832 Receive Status Register Latched #1 Regi

DS3170 DS3/E3 Single-Chip Transceiver 198 of 233 Register Name: E3G832.RSRIE1 Register Description: E3 G.832 Receive Status Register Interrupt Ena

DS3170 DS3/E3 Single-Chip Transceiver 199 of 233 Bit 3: Remote Defect Indication Interrupt Enable (RDIIE) – This bit enables an interrupt if the RD

DS3170 DS3/E3 Single-Chip Transceiver 2 of 233 DETAILED DESCRIPTION The DS3170 is a software-configured, DS3/E3, single-chip transceiver (SCT). The

DS3170 DS3/E3 Single-Chip Transceiver 20 of 233 6.2 DS3/E3 Unframed LIU Mode The frame mode determines the CLAD clock rate, LIU mode and selects B

DS3170 DS3/E3 Single-Chip Transceiver 200 of 233 Bit 0: Framing Error Count Interrupt Enable (FECIE) – This bit enables an interrupt if the FECL bi

DS3170 DS3/E3 Single-Chip Transceiver 201 of 233 Register Name: E3G832.RFECR Register Description: E3 G.832 Receive Framing Error Count Register Re

DS3170 DS3/E3 Single-Chip Transceiver 202 of 233 12 JTAG INFORMATION 12.1 JTAG Description This device supports the standard instruction codes SA

DS3170 DS3/E3 Single-Chip Transceiver 203 of 233 12.2 JTAG TAP Controller State Machine Description This section covers the details on the operat

DS3170 DS3/E3 Single-Chip Transceiver 204 of 233 Capture-DR. Data may be parallel loaded into the Test Data register selected by the current instr

DS3170 DS3/E3 Single-Chip Transceiver 205 of 233 12.3 JTAG Instruction Register and Instructions The instruction register contains a shift regist

DS3170 DS3/E3 Single-Chip Transceiver 206 of 233 CLAMP. All digital output pins output data from the boundary scan parallel output while connectin

DS3170 DS3/E3 Single-Chip Transceiver 207 of 233 12.5 JTAG Functional Timing This functional timing for the JTAG circuits shows: · The JTAG cont

DS3170 DS3/E3 Single-Chip Transceiver 208 of 233 13 PIN CONFIGURATIONS Table 13-1. DS3170 Pin Assignments for 100-Pin LQFP (Sorted by Signal Name)

DS3170 DS3/E3 Single-Chip Transceiver 209 of 233 Table 13-2. DS3170 Pin Assignments for 100-Pin LQFP (Sorted by Pin #) PIN SIGNAL PIN SIGNAL PIN SI

DS3170 DS3/E3 Single-Chip Transceiver 21 of 233 6.3 DS3/E3 Framed POS/NEG Mode FRAME MODE FM[2:0] DS3 C-bit Framed 000 DS3 M23 Framed 001 E3

DS3170 DS3/E3 Single-Chip Transceiver 210 of 233 Table 13-3. DS3170 Pin Assignments for 100-Ball CSBGA (Sorted by Signal Name) SIGNAL BALL SIGNAL

DS3170 DS3/E3 Single-Chip Transceiver 211 of 233 Table 13-4. DS3170 Pin Assignments for 100-Ball CSBGA (Sorted by Ball #) BALL SIGNAL BALL SIGNAL B

DS3170 DS3/E3 Single-Chip Transceiver 212 of 233 Figure 13-1. DS3170 Pin Assignments—100-Ball CSBGA (Top View) 1 2 3 4 5 6 7 8 9 10 A CS_N VS

DS3170 DS3/E3 Single-Chip Transceiver 213 of 233 14 PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current

DS3170 DS3/E3 Single-Chip Transceiver 214 of 233 Figure 14-2. Mechanical Dimensions—100-Pin LQFP

DS3170 DS3/E3 Single-Chip Transceiver 215 of 233 15 PACKAGE THERMAL INFORMATION Table 15-1. Thermal Information for 100-Pin CSBGA PARAMETER VALUE

DS3170 DS3/E3 Single-Chip Transceiver 216 of 233 16 DC ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Input, Bidirection

DS3170 DS3/E3 Single-Chip Transceiver 217 of 233 Table 16-3. Output Pin Drive PIN NAME TYPE DRIVE STRENGTH (mA) TLCLK O 6 TPOS /TDAT O 6 TNEG O

DS3170 DS3/E3 Single-Chip Transceiver 218 of 233 17 AC TIMING CHARACTERISTICS There are several common AC characteristic definitions. These generic

DS3170 DS3/E3 Single-Chip Transceiver 219 of 233 Figure 17-4. Hold, Setup, and Delay Definitions (Falling Clock Edge) ClockSignalt5 t6Signalt7 Fi

DS3170 DS3/E3 Single-Chip Transceiver 22 of 233 6.4 DS3/E3 Unframed POS/NEG Mode The frame mode determines the CLAD clock rate if used as the tran

DS3170 DS3/E3 Single-Chip Transceiver 220 of 233 17.1 Framer Data Path AC Characteristics All AC timing characteristics are specified with a 25 p

DS3170 DS3/E3 Single-Chip Transceiver 221 of 233 Table 17-3. Misc Timing (VDD = 3.3V ±5%, Tj = -40°C to +125°C.) PARAMETER SYMBOL CONDITIONS MIN TY

DS3170 DS3/E3 Single-Chip Transceiver 222 of 233 17.3 Micro Interface AC Characteristics 17.3.1 SPI Bus Mode Table 17-5. SPI Bus Mode Timing SYMBO

DS3170 DS3/E3 Single-Chip Transceiver 223 of 233 Figure 17-7. SPI Interface Timing Diagram NOTE:1. Clock edge reference to data controlled by CP

DS3170 DS3/E3 Single-Chip Transceiver 224 of 233 17.3.2 Parallel Bus Mode The AC characteristics for the external bus interface in parallel mode.

DS3170 DS3/E3 Single-Chip Transceiver 225 of 233 Figure 17-8. Micro Interface Nonmultiplexed Read/Write Cycle D[15:0] RDY t8 t10 CS t6 t12 R

DS3170 DS3/E3 Single-Chip Transceiver 226 of 233 Figure 17-9. Micro Interface Multiplexed Read Cycle D[15:0] RDY t8 t10 CS t6 t12 RD, WR,

DS3170 DS3/E3 Single-Chip Transceiver 227 of 233 17.4 CLAD Jitter Characteristics PARAMETER MIN TYP MAX UNITS Intrinsic Jitter (UIP-P) 0.04 UIP-

DS3170 DS3/E3 Single-Chip Transceiver 228 of 233 Figure 17-10. DS3 Pulse Mask Template Table 17-9. E3 Waveform Test Parameters and Limits PARAMET

DS3170 DS3/E3 Single-Chip Transceiver 229 of 233 Figure 17-11 E3 Waveform Template 0-0.1-0.20.10.20.30.40.50.60.70.80.91.01.11.2TIME (ns)G.703E3TEM

DS3170 DS3/E3 Single-Chip Transceiver 23 of 233 6.5 DS3/E3 Framed UNI Mode FRAME MODE FM[2:0] DS3 C-bit Framed 000 DS3 M23 Framed 001 E3 G.75

DS3170 DS3/E3 Single-Chip Transceiver 230 of 233 17.5.2 LIU Input/Output Characteristics Table 17-10. Receiver Input Characteristics—DS3 Mode (VDD

DS3170 DS3/E3 Single-Chip Transceiver 231 of 233 Table 17-12. Transmitter Output Characteristics—DS3 Modes (VDD = 3.3V ±5%, TA = -40°C to +85°C.)

DS3170 DS3/E3 Single-Chip Transceiver 232 of 233 17.6 JTAG Interface AC Characteristics All AC timing characteristics are specified with a 50 pF c

DS3170 DS3/E3 Single-Chip Transceiver 233 of 233 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circu

DS3170 DS3/E3 Single-Chip Transceiver 24 of 233 6.6 DS3/E3 Unframed UNI Mode The frame mode determines the CLAD clock rate if used as the transmit

DS3170 DS3/E3 Single-Chip Transceiver 25 of 233 7 PIN DESCRIPTIONS Note: In JTAG mode, all digital pins are bidirectional to increase the effective

DS3170 DS3/E3 Single-Chip Transceiver 26 of 233 PIN NAME TYPE FUNCTION BGA LQFP D[2]/SPI_SCLK IO Data [2] / SPI Serial Interface Clock < 10

DS3170 DS3/E3 Single-Chip Transceiver 27 of 233 PIN NAME TYPE FUNCTION BGA LQFP AVSSR PWR Analog Gnd for Receive LIU B5 92 AVSST PWR Analo

DS3170 DS3/E3 Single-Chip Transceiver 28 of 233 PIN NAME TYPE PIN DESCRIPTION TNEG O Transmit Negative AMI / Line OH Mask TNEG: When the port

DS3170 DS3/E3 Single-Chip Transceiver 29 of 233 PIN NAME TYPE PIN DESCRIPTION RPOS / RDAT Iad Receive Positive AMI / Data RPOS: When the port li

DS3170 DS3/E3 Single-Chip Transceiver 3 of 233 Figure 1-2. Block Diagram TSOFO/TDENRLCLKRXPRXNTPOS/TDATTNEGTLCLKDS3/E3TransmitLIUIEEE P1149.1JTAG T

DS3170 DS3/E3 Single-Chip Transceiver 30 of 233 PIN NAME TYPE PIN DESCRIPTION TOHCLK O Transmit Overhead Clock TOHCLK: When the port framer is co

DS3170 DS3/E3 Single-Chip Transceiver 31 of 233 PIN NAME TYPE PIN DESCRIPTION TSOFI I Transmit Start Of Frame Input See Table 9-20. TSOFI: Th

DS3170 DS3/E3 Single-Chip Transceiver 32 of 233 PIN NAME TYPE PIN DESCRIPTION TSOFO / TDEN O Framer Start Of Frame / Data Enable See Table 9-21.

DS3170 DS3/E3 Single-Chip Transceiver 33 of 233 PIN NAME TYPE PIN DESCRIPTION positions of the data on the RSER pin. The signal goes high during

DS3170 DS3/E3 Single-Chip Transceiver 34 of 233 PIN NAME TYPE PIN DESCRIPTION address systems. When it is high the address is fed through the add

DS3170 DS3/E3 Single-Chip Transceiver 35 of 233 PIN NAME TYPE PIN DESCRIPTION GPIO7: This signal is configured to be a general purpose IO pin. GP

DS3170 DS3/E3 Single-Chip Transceiver 36 of 233 PIN NAME TYPE PIN DESCRIPTION AVSSR PWR Analog Ground for receive LIU AVSST PWR Analog Ground

DS3170 DS3/E3 Single-Chip Transceiver 37 of 233 7.3 Pin Functional Timing 7.3.1 Line IO 7.3.1.1 B3ZS/HDB3/AMI Mode Transmit Pin Functional Timing

DS3170 DS3/E3 Single-Chip Transceiver 38 of 233 Figure 7-2. Tx Line IO HDB3 Functional Timing Diagram TLCLKTPOSTNEG(TX DATA)HDB3 CODEWORD(TX LINE)+

DS3170 DS3/E3 Single-Chip Transceiver 39 of 233 Figure 7-4. Rx Line IO HDB3 Functional Timing Diagram RLCLKRPOSRNEG(RX DATA)HDB3 CODEWORD(RX LINE)+

DS3170 DS3/E3 Single-Chip Transceiver 4 of 233 TABLE OF CONTENTS 1 BLOCK DIAGRAMS 2 2 APPLICATIONS 12 3 FEATURE DETAILS 13 3.1 GLOBAL FEATUR

DS3170 DS3/E3 Single-Chip Transceiver 40 of 233 Figure 7-6. Rx Line IO UNI Functional Timing Diagram RLCLKRDATRLVCINC BPV COUNTER TWICE INC BPV COU

DS3170 DS3/E3 Single-Chip Transceiver 41 of 233 Figure 7-10 shows the relationship between the DS3 transmit overhead port pins. Figure 7-10. DS3 Fr

DS3170 DS3/E3 Single-Chip Transceiver 42 of 233 Figure 7-13. DS3 Framed Mode Transmit Serial Interface Pin Timing TCLKO orTCLKIDS3 TSERDS3 TDENTSOF

DS3170 DS3/E3 Single-Chip Transceiver 43 of 233 Figure 7-16. DS3 Framed Mode Receive Serial Interface Pin Timing RCLKO orRCLKIDS3 RSERDS3 RDENRSOFO

DS3170 DS3/E3 Single-Chip Transceiver 44 of 233 expected. If the BURST bit is not set, each data byte will be followed by the control byte(s) for t

DS3170 DS3/E3 Single-Chip Transceiver 45 of 233 Figure 7-23. SPI Serial Port Access For Write Mode, SPI_CPOL = 0, SPI_CPHA = 0 0A13LSBMSBSCKCS*MOSI

DS3170 DS3/E3 Single-Chip Transceiver 46 of 233 Figure 7-27. 16-Bit Mode Write 0x12340x2B0D[15:0]A[10:1]RDWRCSA[0]/BSWAPRDYZZNote: Address 0x2B0 =

DS3170 DS3/E3 Single-Chip Transceiver 47 of 233 Figure 7-29. 8-Bit Mode Write 0x340x120x2B00x2B0D[7:0]A[10:1]A[0]/BSWAPZZZZNote: Address 0x2B0 = 0

DS3170 DS3/E3 Single-Chip Transceiver 48 of 233 Figure 7-31. 16-Bit Mode without Byte Swap 0x1234 0x5678Note: Address 0x2B0 = 0x1234

DS3170 DS3/E3 Single-Chip Transceiver 49 of 233 Figure 7-33. Clear Status Latched Register on Read D[15:0]A[10:1]A[0]/BSWAP0x1C00xFFFF0x1C00x0000ZZ

DS3170 DS3/E3 Single-Chip Transceiver 5 of 233 9.2.5 Gapped Clocks...

DS3170 DS3/E3 Single-Chip Transceiver 50 of 233 Figure 7-35. RDY Signal Functional Timing Write 0x1234 0x00780x2B0 0x3A4D[15:0]A[10:1]A[0]/BSWAPZZZ

DS3170 DS3/E3 Single-Chip Transceiver 51 of 233 8 INITIALIZATION AND CONFIGURATION STEP 1: Check Device ID Code. Before any testing can be done, th

DS3170 DS3/E3 Single-Chip Transceiver 52 of 233 Table 8-1. Configuration of Port Register Settings MODE PORT.CR1 0x040 PORT.CR2 0x042 PORT.CR3 0x04

DS3170 DS3/E3 Single-Chip Transceiver 53 of 233 9 FUNCTIONAL DESCRIPTION 9.1 Processor Bus Interface 9.1.1 SPI Serial Port Mode The external proce

DS3170 DS3/E3 Single-Chip Transceiver 54 of 233 The clear on write mode expects the user to use the following protocol: 1. Read the latched status

DS3170 DS3/E3 Single-Chip Transceiver 55 of 233 Figure 9-1. Interrupt Structure GL.ISR.PISRnPORT.ISR bitSRL bitSRL bitSRL bitSRIE bitSRIE bitSRIE b

DS3170 DS3/E3 Single-Chip Transceiver 56 of 233 9.2.1.1.1 LIU Enabled, Loop Timing Enabled In this mode, the receive LIU sources the clock for bot

DS3170 DS3/E3 Single-Chip Transceiver 57 of 233 9.2.2 Sources of Clock Output Pin Signals The clock output pins can be sourced from many clock sou

DS3170 DS3/E3 Single-Chip Transceiver 58 of 233 Table 9-3 identifies the source of the output signal TLCLK based on certain variables and register

DS3170 DS3/E3 Single-Chip Transceiver 59 of 233 Table 9-4. Source Selection of TCLKO (Internal Tx Clock) SIGNAL LOOPT PORT.CR3 LBM[2:0] (PORT

DS3170 DS3/E3 Single-Chip Transceiver 6 of 233 9.11.2 Features ...

DS3170 DS3/E3 Single-Chip Transceiver 60 of 233 9.2.3.1 Transmit Line Interface Pins Timing Source Selection (TPOS/TDAT, TNEG) The transmit line i

DS3170 DS3/E3 Single-Chip Transceiver 61 of 233 Table 9-7. Transmit Framer Pin Signal Timing Source Select LOOPT LBM[2:0] LIUEN CLADC TFTS VALID T

DS3170 DS3/E3 Single-Chip Transceiver 62 of 233 Table 9-9. Receive Framer Pin Signal Timing Source Select LOOPT LBM[2:0] LIUEN CLADC RFTS VALID TI

DS3170 DS3/E3 Single-Chip Transceiver 63 of 233 Figure 9-4. Example IO Pin Clock Muxing QQSETCLRDINTERNALSIGNALTCLKIPIN INVERTRLCLKPIN INVERTRX LI

DS3170 DS3/E3 Single-Chip Transceiver 64 of 233 reset values. The processor bus output signals are also forced to be HIZ when the RST pin is activ

DS3170 DS3/E3 Single-Chip Transceiver 65 of 233 Table 9-10. Reset and Power-Down Sources PIN REGISTER BITS INTERNAL SIGNALS RST G:RST G:RSTDP P:RS

DS3170 DS3/E3 Single-Chip Transceiver 66 of 233 9.4 Global Resources 9.4.1 Clock Rate Adapter (CLAD) The clock rate adapter is composed of a PLL b

DS3170 DS3/E3 Single-Chip Transceiver 67 of 233 Table 9-12. Global 8 kHz Reference Source Table GL.CR2. G8KIS GL.CR2. G8KRS[1:0] SOURCE 0 00 None

DS3170 DS3/E3 Single-Chip Transceiver 68 of 233 9.4.4 General-Purpose IO Pins There are eight general-purpose IO pins that can be used for general

DS3170 DS3/E3 Single-Chip Transceiver 69 of 233 Table 9-16. GPIO Port Alarm Monitor Select PORT.CR4 GPIO(A/B)[3:0] LINE LOS DS3/E3 OOF DS3/E3 LO

DS3170 DS3/E3 Single-Chip Transceiver 7 of 233 17.1 FRAMER DATA PATH AC CHARACTERISTICS ...

DS3170 DS3/E3 Single-Chip Transceiver 70 of 233 Figure 9-7. Performance Monitor Update Logic GL.SR.GPMSPORT.SR.PMSPORT.CR1.PMUPORT.CR1.PMUM1000011X

DS3170 DS3/E3 Single-Chip Transceiver 71 of 233 Figure 9-8. Transmit Error Insert Logic BERT ERRORINSERTBERT.TEICR.MEIMSBERT.TEICR errorinsertion b

DS3170 DS3/E3 Single-Chip Transceiver 72 of 233 Figure 9-9 highlights where each loopback mode is located and gives an overall view of the various

DS3170 DS3/E3 Single-Chip Transceiver 73 of 233 9.5.1.2 Line Loopback (LLB) Line loopback is enabled by setting PORT.CR4.LBM[2:0] = X10. DLB and L

DS3170 DS3/E3 Single-Chip Transceiver 74 of 233 The sequence will only work when the automatic AIS generation is not enabled. CV and P-bit errors

DS3170 DS3/E3 Single-Chip Transceiver 75 of 233 Table 9-18 lists the LAIS decodes for various line AIS enable modes. Table 9-18. Line AIS Enable Mo

DS3170 DS3/E3 Single-Chip Transceiver 76 of 233 long. The generated BERT signal replaces the data on the TSER pin in framed modes when the BERT is

DS3170 DS3/E3 Single-Chip Transceiver 77 of 233 Table 9-23. RSOFO/RDEN Output Pin Functions FM[2:0] PORT.CR2 RSOFOS PORT.CR3 PIN FUNCTION 0XX (FRM

DS3170 DS3/E3 Single-Chip Transceiver 78 of 233 Table 9-26. Line Mode Select Bits LM[2:0] LINE.TCR.TZSD & LINE.RCR.RZSD LM[2:0] (PORT.CR2) Lin

DS3170 DS3/E3 Single-Chip Transceiver 79 of 233 9.6 DS3/E3 Framer / Formatter 9.6.1 General Description The Receive DS3/E3 Framer receives a unipo

DS3170 DS3/E3 Single-Chip Transceiver 8 of 233 LIST OF FIGURES Figure 1-1. LIU External Connections for the DS3/E3 Port of DS3170 ...

DS3170 DS3/E3 Single-Chip Transceiver 80 of 233 · Arbitrary framing format support – Accepts a signal with an arbitrary framing format. The Line o

DS3170 DS3/E3 Single-Chip Transceiver 81 of 233 Figure 9-13. DS3 Frame Format 680 Bits7 Sub-FramesX1X2P1P2M1M2M3F11F21F31F41F51F61F71F12F22F32F42F5

DS3170 DS3/E3 Single-Chip Transceiver 82 of 233 boundary. The multiframe boundary is found by identifying the three multiframe alignment bits (M-bi

DS3170 DS3/E3 Single-Chip Transceiver 83 of 233 A Loss Of Frame (LOF) condition is declared by the LOF integration counter when it has been active

DS3170 DS3/E3 Single-Chip Transceiver 84 of 233 FEBE errors (C-bit format only) are determined by the C-bits in subframe four (C41, C42, and C43).

DS3170 DS3/E3 Single-Chip Transceiver 85 of 233 Table 9-27. C-Bit DS3 Frame Overhead Bit Definitions BIT DEFINITION X1, X2 Remote Defect Indicati

DS3170 DS3/E3 Single-Chip Transceiver 86 of 233 The bits C31, C32, and C33 are all overwritten with the calculated payload parity from the previous

DS3170 DS3/E3 Single-Chip Transceiver 87 of 233 9.6.5.5.1 Receive C-bit DS3 Frame Format The DS3 frame format is shown in Figure 9-13. X1 and X2 a

DS3170 DS3/E3 Single-Chip Transceiver 88 of 233 more of the indicated alarm conditions is present, and set to one when all of the indicated alarm c

DS3170 DS3/E3 Single-Chip Transceiver 89 of 233 9.6.6.5.1 Receive M23 DS3 Frame Format The DS3 frame format is shown in Figure 9-13. The X1 and X2

DS3170 DS3/E3 Single-Chip Transceiver 9 of 233 Figure 9-13. DS3 Frame Format...

DS3170 DS3/E3 Single-Chip Transceiver 90 of 233 Once all of the E3 overhead bits have been overwritten, the data stream is passed on to error inser

DS3170 DS3/E3 Single-Chip Transceiver 91 of 233 A Change Of Frame Alignment (COFA) is declared when the G.751 E3 framer updates the data path frame

DS3170 DS3/E3 Single-Chip Transceiver 92 of 233 Figure 9-17. G.832 E3 Frame Format FA1EMTRMANRGCFA2530 Byte Payload59 Columns9 Rows Figure 9-18. M

DS3170 DS3/E3 Single-Chip Transceiver 93 of 233 FA1 and FA2 are the Frame Alignment bytes. EM is the Error Monitoring byte used for path error moni

DS3170 DS3/E3 Single-Chip Transceiver 94 of 233 The type of BIP-8 error(s) inserted is programmable (errored BIP-8 bit, or errored BIP-8 byte). An

DS3170 DS3/E3 Single-Chip Transceiver 95 of 233 A Change Of Frame Alignment (COFA) is declared when the G.832 E3 framer updates the data path frame

DS3170 DS3/E3 Single-Chip Transceiver 96 of 233 Table 9-30. Payload Label Match Status EXPECTED RECEIVED STATUS 000 000 Match 000 001 Mismatch 000

DS3170 DS3/E3 Single-Chip Transceiver 97 of 233 The bits in a byte are received MSB first, LSB last. When they are output serially, they are output

DS3170 DS3/E3 Single-Chip Transceiver 98 of 233 9.7.4 Transmit HDLC Overhead Processor The Transmit HDLC Overhead Processor accepts data from the

DS3170 DS3/E3 Single-Chip Transceiver 99 of 233 number of bits between the end flag and the start flag will be an integer number of bytes (flags).