Rainbow-electronics BR24L16FVM-W Manual do Utilizador descarregar pdf (Página 7)

BR24L16-W / BR24L16F-W / BR24L16FJ-W /

Memory ICs

BR24L16FV-W / BR24L16FVM-W

7/25

WP timing

SCL

SDA

HD : WP

STOP BIT

ACKACK

DATA (n)DATA (1)

SU : WP

Fig.6(a) WP TIMING OF THE WRITE OPERATION

SCL

SDA

ACKACK

DATA (n)DATA (1)

HIGH : WP

Fig.6(b) WP TIMING OF THE WRITE CANCEL OPERATION

•

For the WRITE operation, WP must be “LOW” during the period of time from the rising edge of the clock which takes in

D0 of first byte until the end of t

. ( See Fig.6 (a) )

During this period, WRITE operation is canceled by setting WP “HIGH”. ( See Fig.6 (b) )

•

In the case of setting WP “HIGH” during t

, WRITE operation is stopped in the middle and the data of accessing

address is not guaranteed. Please write correct data again in the case.

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Rainbow-electronics BR24L16FVM-W Manual do Utilizador Página 7