Rainbow-electronics AT17F080 Manual do Utilizador

1Features• Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Array

10AT17F040/0803039C–CNFG–11/02Notes: 1. AC test lead = 50 pF.2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from ste

11AT17F040/0803039C–CNFG–11/02Notes: 1. AC test lead = 50 pF.2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from ste

12AT17F040/0803039C–CNFG–11/02Notes: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web si

13AT17F040/0803039C–CNFG–11/02Ordering InformationMemory Size Ordering Code Package Operation Range4-Mbit AT17F040-30CCAT17F040-30BJC8CN4 - 8 LAP20J -

14AT17F040/0803039C–CNFG–11/02Packaging Information8CN4 – LAP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 8CN4, 8-lead (6 x 6 x

15AT17F040/0803039C–CNFG–11/0220J – PLCC 2325 Orchard Parkway San Jose, CA 95131RTITLEDRAWING NO.REV. Notes: 1. This package conforms to JEDEC ref

16AT17F040/0803039C–CNFG–11/0244A – TQFP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm B

17AT17F040/0803039C–CNFG–11/0244J – PLCCNotes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not includ

Printed on recycled paper.© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those expressly contai

2AT17F040/0803039C–CNFG–11/02Pin Configuration8-lead LAP20-lead PLCC87651234DATACLKRESET/OECEVCCSER_ENCEO (A2)GND456781817161514CLKNCRESET/OEPAGESEL1C

3AT17F040/0803039C–CNFG–11/0244 PLCC44 TQFP7891011121314151617393837363534333231302965432144434241401819202122232425262728NCRESET/OEPAGESEL0CENCNCGNDP

4AT17F040/0803039C–CNFG–11/02Block DiagramDevice DescriptionThe control signals for the configuration memory device (CE, RESET/OE and CLK)interface di

5AT17F040/0803039C–CNFG–11/02DATA Three-state DATA output for configuration. Open-collector bi-directional pin forprogramming.CLK Clock input. Used to

6AT17F040/0803039C–CNFG–11/02RESET/OE Output Enable (active High) and RESET (active Low) when SER_EN is High. A Lowlevel on RESET/OE resets both the a

7AT17F040/0803039C–CNFG–11/02FPGA Master Serial Mode SummaryThe I/O and logic functions of any SRAM-based FPGA are established by a configura-tion pro

8AT17F040/0803039C–CNFG–11/02Absolute Maximum Ratings*Operating Temperature... -4°C to +85°C*NOTICE: Stresses beyon

9AT17F040/0803039C–CNFG–11/02AC CharacteristicsAC Characteristics when CascadingCERESET/OECLKDATATSCETLCTHCTCACTOETCETOHTHOETSCETHCETDFTOHCERESET/OECL