
62
7511B–SCR–10/05
Reset value = 0x 1111 1111
Table 44. SLEW_CTRL_1(Slew control for SC1 and SC2)
7 6 5 4 3 2 1 0
CCLK2_SLEW_CT
RL1
CCLK2_SLEW_CT
RL0
CIO2_SLEW_CT
RL1
CIO2_SLEW_CT
RL0
CCLK1_SLEW_CT
RL1
CCLK1_SLEW_CTR
L0
CIO1_SLEW_CTR
L1
CIO1_SLEW_CT
RL0
Bit Number Bit Mnemonic Description
7-6
CCLK2_SLEW_CTRL[1-0]
0 0: Mode 1 (optimum for CVCC2=5V)
0 1: Mode 2 (optimum for CVCC2=3V)
1 0: Mode 3 (optimum for CVCC2=1.8V)
1 1: Automatic mode
The reset value is 11.
5-4
CIO2_SLEW_CTRL[1-0]
0 0: Mode 1 (optimum for CVCC2=5V)
0 1: Mode 2 (optimum for CVCC2=3V)
1 0: Mode 3 (optimum for CVCC2=1.8V)
1 1: Automatic mode
The reset value is 11.
3-2
CCLK1_SLEW_CTRL[1-0]
0 0: Mode 1 (optimum for CVCC1=5V)
0 1: Mode 2 (optimum for CVCC1=3V)
1 0: Mode 3 (optimum for CVCC1=1.8V)
1 1: Automatic mode
The reset value is 11.
1-0
CIO1_SLEW_CTRL[1-0]
0 0: Mode 1 (optimum for CVCC1=5V)
0 1: Mode 2 (optimum for CVCC1=3V)
1 0: Mode 3 (optimum for CVCC1=1.8V)
1 1: Automatic mode
The reset value is 11.
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