Rainbow-electronics ATV750BL Manual do Utilizador descarregar pdf (Página 10)

ATV750B(L)

0301I–08/01

Power-up Reset The registers in the ATV750B(L) is designed to reset during power-up. At a point delayed

slightly from V

crossing V

RST

, all registers will be reset to the low state. The output state will

depend on the polarity of the output buffer.

This feature is critical for state machine initialization. However, due to the asynchronous

nature of reset and the uncertainty of how V

actually rises in the system, the following condi-

tions are required:

1. The V

rise must be monotonic,

2. After reset occurs, all input and feedback setup times must be met before driving the

clock terms or pin high, and

3. The clock pin, or signals from which clock terms are derived, must remain stable during

Parameter Description Typ Max Units

Power-up Reset Time 600 1000 ns

RST

Power-up Reset Voltage 3.8 4.5 V

Pin Capacitance

f = 1 MHz, T = 25°C

(1)

Typ Max Units Conditions

58 pF V

= 0V

OUT

68 pF V

OUT

= 0V

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 18 19

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Rainbow-electronics ATV750BL Manual do Utilizador Página 10